Hi All,
i went through this link
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html
and related a53 vector table implementation.
in this regard, i have a question
1. Say a processor gets stuck in exception handler due…
Hi all,
I have two A15 CPUs and 1GByte of DRAM memory. I want to dedicate 0.5GByte of memory to each CPU. Would the following system work?
(A15) (A15)
| |
----CCI----…
In A7 platform with TZ extension , I know that there is a virtual MMU for non secure world, and I think it should be enabled after entering non secure world.
But the most confusing thing is that what has to be done with cache-----clean , invalidate or…
This question was asked in the 'How to optimize a system with the latest ARM DynamIQ processors' webinar. You can view all other related questions in this blog post.
Hello everyone. I'm trying to understand how to create and make work two separate baremetal programms on two cores of cortex-a9. I'm using Cyclone V SoC. DS-5, arm compiller 5, DE1-SoC board by terasic. I already understand how to work with main core…
I would like to get some confirmation that if we replace A53/A72 with A7/A9 while the SoC architecture is still based on ARM v8 bus & IPs (e.g. CCI400, NIC400, TZC400, GIC500, BP141), does such design feasible and workable?
