• Exception handlers and interrupt

    RCReddy
    RCReddy

    Hi All,

            i went through this link

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471g/BABGCFHB.html

    and related a53 vector table implementation.

    in this regard, i have a question

    1. Say a processor gets stuck in exception handler due…

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • Is the Corelink SSE-200 Subsystem available for Cortex M23?

    Mike EFTIMAKIS
    Mike EFTIMAKIS

    This question was raised in the 'How to implement a secure IoT system on ARMv8-M' webinar, view all the questions in the round up blog post. 

     
    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • Can you explain why you propose having two cores in your CoreLink SSE-200?

    Mike EFTIMAKIS
    Mike EFTIMAKIS

    This question was raised in the 'How to implement a secure IoT system on ARMv8-M' webinar, view all the questions in the round up blog post. 

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • How did you measure the Instruction cache efficiency? Just code execution from Flash? Reading data from Flash? Programming data to Flash?

    Mike EFTIMAKIS
    Mike EFTIMAKIS

    This question was raised in the 'How to implement a secure IoT system on ARMv8-M' webinar, view all the questions in the round up blog post. 

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • GIC 500 :: Not able to find the definition for GICD_IROUTERn register

    danish259
    danish259

    Can someone please point me to the documentation where I can find the definition for GICD_IROUTERn register. I see it mentioned in DDI0516B_gic5000_r0p0_trm but not the complete definition.

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • GIC500 :: Not able to disable Affinity Routing

    danish259
    danish259

    I'm not able to disable the affinity routing (i.e. ARE_S and ARE_NS bits being set always). Reset value of GICD_CTLR register is 0x30.

    Actually I want to forward the interrupt from Distributor to multiple Cores but seems to use ITARGETSR, affinity…

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
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