How to identify all the coresight ROM tables present in an SoC? Can APB-AP ROM table and AHB ROM tables co-exist as part of a single ROM table in the system memory?
Embedded Trace Fifo(ETF) in Hardware FIFO mode flushing trace data
Hi there,
good morning.
I am using TMC as Embedded Trace Fifo and testing it for FULL condition.
Is there any way, I can stop TMC from not reading the trace data that is written in the SRAM of ETF?
So that eventually it gets full setting the FULL bit in STS…
- over 4 years ago
- System
- SoC Design forum
Arm Coresight : Post process for trace
How does post process work for trace verification ?
- over 2 years ago
- System
- SoC Design forum
Arm Coresight:ETB
The ETB/ETF sitting in the trace path may be used as a circular buffer (capture) trace sink or configured into hardware FIFO mode or software FIFo mode. So how to choose which mode need to br programme for which trace ??
- over 2 years ago
- System
- SoC Design forum
Coresight 400 tool installation and IP generation
HI all,
I am new to this tool. I have following queries
1. To install this, do we requires all the tools the verified in 'verify_install_cssoc.sh'
2. Becuase i dont have all the tools, i just commented the code which source 'verify_install_cssoc…
- over 1 year ago
- System
- SoC Design forum
coresight devices registration problem
Hi i compiled the kernel code and flashed the image in ARM64 architecture juno board but the coresight devices are not being shown up in /sys/bus/coresight/devices directory. I am not getting the problem ?
- over 1 year ago
- System
- SoC Design forum