• AXI4 Bus Bandwidth/Data Transfer increase

    willo144
    willo144

    Hello,

    I am doing research with an Ultra-Embedded Implementation of a RISC-V Processor in gem5.  My team is using an Oracle Virtual Machine to run testbenches and benchmarks for our research motivation.  As part of our research, I have been tasked with…

    • 2 months ago
    • System
    • SoC Design forum

  • AXI fixed burst to a slave with narrow data width

    Sana
    Sana

    Hi,

    I have an AXI master with data width 64, and an AHB slave of data width 32. What would happen when there is a 64bit FIXED burst READ (i.e., asize=3)to an address 0X100 of the slave? 

    Would the the data be read from 0x100 only, with data[63:32] always…

    • 9 months ago
    • System
    • SoC Design forum

  • AMBA AXI Write response

    Sai Krishna
    Sai Krishna
    I am just going through the specs of AMBA AXI.
    I've few questions.It will be great if anybody clarify
    1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response for each beat in a Read burst ?
    2) How to terminate…
    • over 6 years ago
    • System
    • SoC Design forum

  • applications of amba axi

    abilash abilash
    abilash abilash
    Note: This was originally posted on 7th February 2007 at http://forums.arm.com

    hello, i have read the whole of the axi protocol. i would like to know the applications of the protocol. is it anywhere used in the real time applications or some specific devices…
    • over 6 years ago
    • System
    • SoC Design forum

  • AXI write strobes

    jameskim jameskim
    jameskim jameskim
    Note: This was originally posted on 21st February 2007 at http://forums.arm.com

    the AXI spec says:

    10.1 About unaligned transfers
    [...]
    For any burst that is made up of data transfers wider than one byte, it is possible that the first bytes that have to be…
    • over 6 years ago
    • System
    • SoC Design forum

  • Basics: C programming for ARM - AHB transfers

    joewu joewu
    joewu joewu
    Note: This was originally posted on 18th September 2007 at http://forums.arm.com

    Hello,
    Would someone please help me about the next basic things?
    I have programed microcontrollers in the past but now I need to work with ARM processors and need some basic…
    • over 6 years ago
    • System
    • SoC Design forum

  • AXI Read/Write ordering

    Randy Pascarella
    Randy Pascarella
    Note: This was originally posted on 24th October 2007 at http://forums.arm.com

    Hello,
       Section 8.6 of the AXI spec says that reads and writes have no ordering restrictions between them.  It then says that if a RAW dependency exists, the master must wait…
    • over 6 years ago
    • System
    • SoC Design forum

  • More AXI write/read ordering

    Randy Pascarella
    Randy Pascarella
    Note: This was originally posted on 25th October 2007 at http://forums.arm.com

    In another posting, a scenario given was with a RAW hazard where a bufferable write was followed by a read to an overlapping address.  Sounds like the master's assumption upon…
    • over 6 years ago
    • System
    • SoC Design forum

  • AXI Cacheable vs. Bufferable

    Randy Pascarella
    Randy Pascarella
    Note: This was originally posted on 19th November 2007 at http://forums.arm.com

    If an AXI slave acting as a bridge has accepted a bufferable (ACACHE[0]) and cacheable (ACACHE[1]) write and responded with BRESP, is it required to flush this buffered write…
    • over 6 years ago
    • System
    • SoC Design forum

  • How to go from 32-bit to 64-bit AHB data bus

    tamo tamo
    tamo tamo
    Note: This was originally posted on 21st November 2007 at http://forums.arm.com

    Hi,
    I have to write a C program for an ARM processor that has a 64-bit data bus (ARM11, Cortex-R4) and to perform some simulations afterward (Verilog). So far I have only worked…
    • over 6 years ago
    • System
    • SoC Design forum

  • AXI protocol

    neha004
    neha004
    Note: This was originally posted on 30th December 2007 at http://forums.arm.com

    Can anyone tell me the exact explanation and differnce between out of order completion and write data interleaving  in detail...as i`m very confused with these terms
    • over 6 years ago
    • System
    • SoC Design forum

  • Confusion over AMBA AHB hsize[] signal definition

    davemac2 davemac2
    davemac2 davemac2
    Note: This was originally posted on 26th February 2008 at http://forums.arm.com

    After reading the AMBA AHB spec rev 2, I am still confused over the relationship of the HSIZE[2:0] signal and the implemented bus width on an interface.  If an AHB bus is implemented…
    • over 6 years ago
    • System
    • SoC Design forum

  • AHB Multilayer

    Jesuraj vinoth Joseph
    Jesuraj vinoth Joseph
    Note: This was originally posted on 30th April 2008 at http://forums.arm.com

    In the multilayer environment,  i found a interconnect matrix with interface signals on the Master side having a hsel signal. Can anyone specify the significance of it. A basic…
    • over 6 years ago
    • System
    • SoC Design forum

  • AXI locked access

    spark spark
    spark spark
    Note: This was originally posted on 29th May 2008 at http://forums.arm.com

    Does a locked request on either the read or write channel cause both channels to be locked? For example, one master request a locked write transaction to a slave, the read channel…
    • over 6 years ago
    • System
    • SoC Design forum

  • AHB WRAP address boundaries

    myarm myarm
    myarm myarm
    Note: This was originally posted on 18th June 2008 at http://forums.arm.com

    AMBA spec (v2.0) only shows how the addresses wrap when hsize = 2 (word). Is it because the address boundary remains the same for each WRAP4, WRAP8, and WRAP16 cases? Or, should…
    • over 6 years ago
    • System
    • SoC Design forum

  • AHB Bufferable/Non-bufferable write

    Hariprem Arora
    Hariprem Arora
    Note: This was originally posted on 12th September 2008 at http://forums.arm.com

    Hi,

    Please clarify the following issue related to AHB write:

    If HPROT[2] = 1, AHB write is bufferable and we need to provide OKAY response as soon as the AHB slave interface…
    • over 6 years ago
    • System
    • SoC Design forum

  • AMBA AHB HSPLITx signal.....

    LEO LEO
    LEO LEO
    Note: This was originally posted on 30th September 2008 at http://forums.arm.com

    Hi guys...

    I am trouble again..... :wacko:

    My question is :

    If slave 0 gives split error to two masters say master 0 and master 1...
    Now slave can generate Hsplitx for both masters…
    • over 6 years ago
    • System
    • SoC Design forum

  • AHB response relation with data

    Hariprem Arora
    Hariprem Arora
    Note: This was originally posted on 30th September 2008 at http://forums.arm.com

    Hi,

    I have an issue regarding AHB responses relation
    with data in case of AHB write transfers.

    As we know that the address phase of any transfer occurs during
    the data phase…
    • over 6 years ago
    • System
    • SoC Design forum

  • Wrap address usage?

    LEO LEO
    LEO LEO
    Note: This was originally posted on 18th October 2008 at http://forums.arm.com

    Hello guys..

    I am working on AMBA AHB...
    and came across the wrap address term...
    Can you tell me that which kind of application need to do transfer using wrap address?
    • over 6 years ago
    • System
    • SoC Design forum

  • questions about APB advantages

    jiunyan jiunyan
    jiunyan jiunyan
    Note: This was originally posted on 8th November 2008 at http://forums.arm.com

    Hi! dear all  :lol:
    Some APB advantages are listed in AMBA 2.0 spec. They are

    "¢ performance is improved at high-frequency operation
    "¢ performance is independent of…
    • over 6 years ago
    • System
    • SoC Design forum

  • quiery about AHB burst mode

    Harsharaj ellur
    Harsharaj ellur
    Note: This was originally posted on 19th November 2008 at http://forums.arm.com

    hi,

    in the AHB burst mode is it the Master that drives consecutive address to slave, or is it that the master only sends the start address and Slave using this, HSIZE and HBURST…
    • over 6 years ago
    • System
    • SoC Design forum

  • AHB Arbiter

    vishalrane vishalrane
    vishalrane vishalrane
    Note: This was originally posted on 21st November 2008 at http://forums.arm.com

    Y is it necessary to provide HADDR input to the arbiter in AHB bus protocol ?
    • over 6 years ago
    • System
    • SoC Design forum

  • AHB Busy states...

    LEO LEO
    LEO LEO
    Note: This was originally posted on 24th November 2008 at http://forums.arm.com

    Hello guys....

    If master is doing transfer of fixed length burst and last address is driven on bus...
    Can master drive htrans to BUSY.. at same time to put data on data bus?…
    • over 6 years ago
    • System
    • SoC Design forum

  • app crashes when compiled with OTime O3 using RVDS 4.0

    pradipig pradipig
    pradipig pradipig
    Note: This was originally posted on 1st December 2008 at http://forums.arm.com

    Hi,
    I am using RVDS 4.0 trial version. When I compile my app using OTime O3 compiler flag, the application crashes. But if I specify O2 then it is working properly.

    My compiler…
    • over 6 years ago
    • System
    • SoC Design forum

  • AHB split retry response

    abc_xyz pqr_def
    abc_xyz pqr_def
    Note: This was originally posted on 9th December 2008 at http://forums.arm.com

    IN AMBA AHB , there are split and retry response. These are 2 cycle responses.
    whole SPLIT sequence is given in the spec. but my doubt is in which scenario slave
    has to to issue…
    • over 6 years ago
    • System
    • SoC Design forum
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