AMBA AXI Write response

Sai Krishna

I am just going through the specs of AMBA AXI.
I've few questions.It will be great if anybody clarify
1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response for each beat in a Read burst ?
2) How to terminate…

over 6 years ago
System
SoC Design forum

applications of amba axi

abilash abilash

Note: This was originally posted on 7th February 2007 at http://forums.arm.com

hello, i have read the whole of the axi protocol. i would like to know the applications of the protocol. is it anywhere used in the real time applications or some specific devices…

over 6 years ago
System
SoC Design forum

AXI write strobes

jameskim jameskim

Note: This was originally posted on 21st February 2007 at http://forums.arm.com

the AXI spec says:

10.1 About unaligned transfers
[...]
For any burst that is made up of data transfers wider than one byte, it is possible that the first bytes that have to be…

over 6 years ago
System
SoC Design forum

AXI Read/Write ordering

Randy Pascarella

Note: This was originally posted on 24th October 2007 at http://forums.arm.com

Hello,
Section 8.6 of the AXI spec says that reads and writes have no ordering restrictions between them. It then says that if a RAW dependency exists, the master must wait…

over 6 years ago
System
SoC Design forum

More AXI write/read ordering

Randy Pascarella

Note: This was originally posted on 25th October 2007 at http://forums.arm.com

In another posting, a scenario given was with a RAW hazard where a bufferable write was followed by a read to an overlapping address. Sounds like the master's assumption upon…

over 6 years ago
System
SoC Design forum

AXI Cacheable vs. Bufferable

Randy Pascarella

Note: This was originally posted on 19th November 2007 at http://forums.arm.com

If an AXI slave acting as a bridge has accepted a bufferable (ACACHE[0]) and cacheable (ACACHE[1]) write and responded with BRESP, is it required to flush this buffered write…

over 6 years ago
System
SoC Design forum

AXI protocol

neha004

Note: This was originally posted on 30th December 2007 at http://forums.arm.com

Can anyone tell me the exact explanation and differnce between out of order completion and write data interleaving in detail...as i`m very confused with these terms

over 6 years ago
System
SoC Design forum

AXI locked access

spark spark

Note: This was originally posted on 29th May 2008 at http://forums.arm.com

Does a locked request on either the read or write channel cause both channels to be locked? For example, one master request a locked write transaction to a slave, the read channel…

over 6 years ago
System
SoC Design forum

the usage of WSTRB signal

Dong Luo

Note: This was originally posted on 26th February 2009 at http://forums.arm.com

Hi All,
I was going through the AMBA AXI specs, but I have some questions about the usage of the WSTRB signal. In the middle of a burst, can some bits of WSTRB be low? Again…

over 6 years ago
System
SoC Design forum

Write Data Interleaving - AXI

Amaresh Chaligeri

Note: This was originally posted on 19th March 2009 at http://forums.arm.com

Hello,

Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec.
[Chapter 8.5 Write data interleaving]

"The order…

over 6 years ago
System
SoC Design forum

STM(System Trace Macrocell)

dudu8

Can i observe the 1KB data that it is written over the STM AXI interface from STM ATB BUS ?

what i mean is that i want to send a 1KB data from STM AXI and observe it from the STM ATB with MIPI STPv2 format.

over 3 years ago
System
SoC Design forum

Project on AXI Bus.

Naina

Hi,

I am working on AXI bus for my college project. For my work I have to add something new in existing architecture. Can someone provide me idea for my work?

over 2 years ago
System
SoC Design forum