I have one question for QoS with AXI4:
Can one master have multiple QoS values?
Meaning one master issues requests with different QoS values but all with same AXI ID and the interconnect network arbitrates between these requests based on QoS value and…
Hi,
I'm getting two AXI4 protocol assertion errors.
For axi4_errm_wlast_stable, I can see why it's flagging an error but functionally it shouldn't be a problem.
The WREADY =1 for one more cycle when though WVALID=0 and WLAST=0.
Is this a…
The AXI protocol description states for modifiable transactions (ARCACHE[1] is asserted):
"a read transaction can fetch more data than required"
To me, this can be interpreted in two ways:
i am sending data "NEWDATAA" which is 8 bytes. and starting address is 5, which is unaligned address then whether my data is loss or not . please explain how the whole transfer will happens. how the strobe will works. is my data start with aligned…
In the spec it is mentioned that AXI4 supports high-bandwidth, high-frequency and low-latency operation. How to justify this? What is the meaning of bandwidth in this context? What are the values of bandwidth and frequency? How they decide the operating…
I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.
Eg. Burst length- Two , Burst size 16 bytes.
Please give me answers for different types of data bus width say for bus width …
