Hello,
I am doing research with an Ultra-Embedded Implementation of a RISC-V Processor in gem5. My team is using an Oracle Virtual Machine to run testbenches and benchmarks for our research motivation. As part of our research, I have been tasked with…
Hi,
I have an AXI master with data width 64, and an AHB slave of data width 32. What would happen when there is a 64bit FIXED burst READ (i.e., asize=3)to an address 0X100 of the slave?
Would the the data be read from 0x100 only, with data[63:32] always…
address = 0x07
transfer size = 32 bit
burst type = INC
Burst length = 4 transfers
Can you please explain this example of unaligned word transfer on 64-bit bus.
Why the second transfer started at 8 and not from C?
According to what I read in AXi spec sheet, AxLOCK signals are used by the Masters for a locked access to a slave and it's the arbiter/interconnect which takes care of the AxLOCK signal.
Am I right when I say that, "Slave doesn't care if it's Locked…
Can i observe the 1KB data that it is written over the STM AXI interface from STM ATB BUS ?
what i mean is that i want to send a 1KB data from STM AXI and observe it from the STM ATB with MIPI STPv2 format.
Hello ,
I am new to AXI protocol. Though I have read the document of AXI , but have some doubts on it. I have made run a write sequence (only from AXI to get the better understanding ) Please have a look at the following waveform.
In this diagram …
i read the specification of AXI 4 protocol. i want to know what action will be performed by the master when it receive okay,exokay,slverr or decerr. okay and exokay says that the transfer is completed either by normal access and by the exclusive access…
This is regarding the AXI3 write data interleaving. I understand how the write data interleaving works when AWID=WID when a slave is accessed by multi masters or a single master which can generate multiple outstanding transactions. But I have a query on…
Hello,
A couple of further details on the question.
Let's assume that I have a 64-bit data bus and a 32-bit address bus.
A master issues a WRAP burst with AWADDR[31:0] = 32'd8 and AWSIZE[2:0] = 3'b110. That is, the start address is 8 and the beat…
when I say partial word access, I mean 16-bit (two byte) or 8-bit (byte) read/write.
Background:
In one of our recent projects, Cyclone V SoC is used to replace 386 CPU in an existing product.
I am responsible for the board and FPGA design. Another software…
In AHB, we have split and retry responce, but it doesn't exist in AXI, why ?
Hi,
I have a question about the correct behavior when performing a narrow read with an unaligned address; consider the following scenario:
- 32 bit data bus
- address x0001
- length 0 (1 beat)
- size 1 (2 byte)
My interpretation of the spec is that in…
I am implementing Read Modified Write on SRAM through AXI. What is the role of awsize and wstrbe?
Say data width is 64 bits, and awsize is set to support 64-bits, but the underlying wstrbe are only valid for lower 32-bits (8'b0000_1111). Does this candid…
In AXI Write how the handshake between AW channel and B channel is taken care.
Standard says that
"the slave must wait for both WVALID and WREADY to be asserted before asserting BVALID"
Does that means BVALID will never be asserted in the same…
I have one question for QoS with AXI4:
Can one master have multiple QoS values?
Meaning one master issues requests with different QoS values but all with same AXI ID and the interconnect network arbitrates between these requests based on QoS value and…
