[APB] Assert timing of PSTRB and PPROT

Taichi Ishitani

Hi All,

I have a question about assert timing of PSTRB and PPROT.

I think APB4 spec (IHI0024C_amba_apb_protocol_spec.pdf) does not describe when PSTRB and PPROT should be asserted.
I guess these signals should be asserted while PSEL is high like PADDR…

Answered

1 month ago
System
SoC Design forum

questions about APB advantages

jiunyan jiunyan

Note: This was originally posted on 8th November 2008 at http://forums.arm.com

Hi! dear all

Some APB advantages are listed in AMBA 2.0 spec. They are

"¢ performance is improved at high-frequency operation
"¢ performance is independent of…

over 6 years ago
System
SoC Design forum

ARM Cortex ICode, DCode, System buses

Felix Varghese

Note: This was originally posted on 26th February 2009 at http://forums.arm.com

I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?

…

over 6 years ago
System
SoC Design forum

AMBA

vish9746

How is it possible for AMBA bus protocol to communicate between ASB bus and APB bus,if they operate in different frequency's? ASB is high performance high frequency bus and APB is low performance low frequency bus..how that communication is happening…

Answered

over 1 year ago
System
SoC Design forum

APB3 Slave responding when PSEL = 0

vshankar11

Hello All,

Here at IP Level verification we have no issues as the Master APB does not latch the PREADY, but at SOC Level with multiple APB Slaves

The Master performs some transaction with APB SLAVE 1 and before switching to APB SLAVE 2 , it disables the…

Answered

over 1 year ago
System
SoC Design forum

Assertion for Multiple Transfer on APB Bus

Rakesh Venkatesan

Hi,

Can you please help me in writing assertions to take care on multiple transfer in APB bus?

Thanks,

Rakesh

over 1 year ago
System
SoC Design forum

How can I get IP-XACT descriptions of CMSDK components?

Steven Dennis

We use IP-XACT based automation tools, mainly for register views, so need IP-XACT description of the APB registers for the CMSDK components.

Answered

over 4 years ago
System
SoC Design forum

Can PENABLE be removed from APB as it seems redundant at IO level and same logic can be taken care of internally by Master and Slave ?

architt

PENABLE indicates the second and subsequent cycles of an APB transfer till PREADY goes HIGH.

APB transfer can be considered as complete when PSEL==1 and PREADY==1 ignoring PENABLE==1 and PREADY==1 should be considered only after second and subsequent cycles…

over 3 years ago
System
SoC Design forum

AXI AHB APB quick reference cheat sheet

MattHutson

Hi,

I have tried to find a quick reference for AXI, AHB & APB to no avail, and after having to flit between the various documents and tables, I eventually created my own.

So not sure of the legal ramifications of posting this elsewhere and whether…