Hi,

I have a question about the correct behavior when performing a narrow read with an unaligned address; consider the following scenario:

- 32 bit data bus

- address x0001

- length 0 (1 beat)

- size 1 (2 byte)

My interpretation of the spec is that in…

I am implementing Read Modified Write on SRAM through AXI. What is the role of awsize and wstrbe?

Say data width is 64 bits, and awsize is set to support 64-bits, but the underlying wstrbe are only valid for lower 32-bits (8'b0000_1111). Does this candid…

PENABLE indicates the second and subsequent cycles of an APB transfer till PREADY goes HIGH.

APB transfer can be considered as complete when PSEL==1 and PREADY==1 ignoring PENABLE==1 and PREADY==1 should be considered only after second and subsequent cycles…

In AXI Write how the handshake between AW channel and B channel is taken care.

Standard says that 

"the slave must wait for both WVALID and WREADY to be asserted before asserting BVALID"

Does that means BVALID will never be asserted in the same…

I have one question for QoS with AXI4:

Can one master have multiple QoS values?

Meaning one master issues requests with different QoS values but all with same AXI ID and the interconnect network arbitrates between these requests based on QoS value and…

Hi,

I'm getting two AXI4 protocol assertion errors.

For axi4_errm_wlast_stable, I can see why it's flagging an error but functionally it shouldn't be a problem.

The WREADY =1 for one more cycle when though WVALID=0 and WLAST=0. 

Is this a…

Hi,

Facing the issue:
"MBERROR :  AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave"

Here is the Inputs:

We are using the custom SOC, in which we are testing the CLCD controller(IP ARM PL111)
connected…

The AXI protocol description states for modifiable transactions (ARCACHE[1] is asserted):

"a read transaction can fetch more data than required"

To me, this can be interpreted in two ways:

1. The RVALID signal of the slave can be asserted for…

Hi,

I am working on AXI bus for my college project. For my work I have to add something new in existing architecture. Can someone provide me idea for my work? 

i am sending data "NEWDATAA"  which is 8 bytes. and  starting address is 5, which is unaligned address then whether my data is loss or not . please explain how the whole transfer will happens. how the strobe will works. is my data start with aligned…

can any1 explain me completion response and ordering in chi protocol??? and any good and easy source to understand chi protocol except spec..????

Hi,

From hardware perspective, what's the purpose of WACK and RACK and how does it affect the ACE protocol ?

I can see that the specification says the master issues these two signals to indicate to the interconnect that Write and Read transactions…

I would like to get some confirmation that if we replace A53/A72 with A7/A9 while the SoC architecture is still based on ARM v8 bus & IPs (e.g. CCI400, NIC400, TZC400, GIC500, BP141), does such design feasible and workable?

Hi,

The AMBA5 spec for ACE5 shows some new signals versus ACE4 :

VAWQOSACCEPT

VARQOSACCEPT

AWAKEUP

ACWAKEUP

SYSCOREQ

SYSCOACK

How are these used in an SOC system ?

For example, I think but I'm not usre if VAWQOSACCEPT, VARQOSACCEPT is output by each slave…

Hi ARM/arktos,

Seems like this online discussion is not working properly.

I ask a question, you reply, and if I reply the discussion tool doesn't echo back my reply by email.

So most likely you may not see it.

Below is my reply to your answer to my…

Hi,

1) ARBAR/AWBAR

These two signals are mentioned : ARBAR, AWBAR but in the AMBA5 spec F2.1 Signal Matrix, these signals are listed as "N" (must not be present), page 419 and 420 of 440 pages. 

So are these signals used on the ACE5 interface…

Hi,

I'm trying to add some checks for AXI5 / AXI5 -Lite protocol.

When Untranslated Transaction is TRUE, do all of the signals

A[R/W]MMUSECSID

A[R/W]MMUSID

A[R/W]MMUSSIDV

A[R/W]MMUSSID

A[R/W]MMUATST

need to be defined and used together.

For example…

In the spec it is mentioned that AXI4 supports high-bandwidth, high-frequency and low-latency operation. How to justify this?  What is the meaning of bandwidth in this context? What are the  values of bandwidth and frequency? How they decide the operating…

Hi,

   I need a clarification on PENABLE with respect to PREADY. 
   1) Can pready remain high for more than one cycle?
   2) Does PENABLE from the master has to look for PREADY going low to deassert or it should go low the cycle next to the assertion of PREADY…

I want to know what happens in these scenarios :
1) Assume Master1 (M1) is doing locked access, if locked access fails before M1 does unlocking transaction what is the response to the M1?
2) Assume M1 is doing locked transaction, if other Master2 (M2)…

Dear Community,

I am reading AXI speck from the ARM, please help better understand the AXI, by answering my questions regarding to Burst transaction.

a)
I cannot clearly understand the meaning of Burst size signals - ARSIZE and AWSIZE.
When there are Bust…

Hi,

I was reading the CHI architecture specification but there is no mention of electrical characteristics such as

the clock frequency for the CHI interface.

What is the max and min frequency for CHI interface ?

Thanks,

David

Hi,

I assume CHI needs to either pipeline or implement something like the AXI register slice to support long distance connections.

Please confirm and where can I find relevant information for this topic.

Thanks,

David

P189, 5.2.1 Dataless transaction without memory update

Why does RN-F0 transition I->UC, rather than UCE or UD? After MakeUnique, RN-F0 has obtained the right to modify the cache line by discarding all other copies, dirty or not, in other caches. The purpose…