Hi,

In my design I am having a scenario where my Hsel goes low during the data phase of a transfer and Hready goes high one cycle after that? (i.e hready high during address phase low during data phase and high again in the follwoing cycle 1->0 -> 1)…

Hi All ,

                      The following figure shows the INCR4 burst transaction.

Here the address increment is happening in each clk cycle  As per AHB protocol Single outstanding address is allowed.

What are the possible adjustment has to be made for this transaction…

Difference between axi_4 and axi4_alite?

Hi All ,

            Can anyone please tell the difference btw AXI3 and AXI4.

Regards

Muthuvenkatesh

what are the possible values of strobe for a half word transfer in AXI4 lite? 

Are these following values on WSTRB valid ?

-1001

-0101

-1010

hi,

what are the purpose of interconnect..?and why we nedd address routing table..in axi4

Hi,

 I am developing a RTL code for AHB lite - AXI bridge. I want to understand what are the possible error scenarios in AHB?

1.I can think of invalid address as the only case. Is there any other scenario?

2. I am performing a INCR4 transfer on AHB side…

Hi,

I am creating a systemC model for a peripheral which has an AXI4 interface.

Is there a bit and pin accurate AXI4 SystemC model similar to the ones available for OCP?

Is it available from ARM, a ThirdParty vendor, or the opensource community?

Hello I want to know the calculation for

HSIZE=2 and Wrap 8

and starting address is 0x4

and how we are doing alignment ???

I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.

Eg. Burst length- Two , Burst size 16 bytes.

Please give me answers for different types of data bus width say for bus width …