Hi,

In AMBA AHB:-

     For two clock cycle SPLIT or RETRY response, hgrant must be low after 1st clock cycle of SPLIT or RETRY response.

   q)  For two clock cycle ERROR response, is it mandatory of hgrant must be low after 1st clock…

What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles.

Thanks

I am a Digital Verification Design Engineer.

Currently, I am in the process of developing an UVM Test Bench for AHB 2.0.

I have following questions.

1) From AHB Master side, Can BUSY cycles be inserted in middle of INCR16 burst?

2) From AHB Master side,…

Can i observe the 1KB data that it is written over the STM AXI interface from STM ATB BUS ?

what i mean is that i want to send a 1KB data from STM AXI and observe it from the STM ATB with MIPI STPv2 format.