• Why does AHB or APB support only 16 slave devices?

    Ravindran
    Ravindran

    I would like to know why only 16 slave device select lines are present in the AHB and APB bus architectures.

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • Working frequency on AMBA- APB,AHB, AXI

    Ujjwal.K64
    Ujjwal.K64

    Hii,

    Greetings !!

    I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

    Please someone help me out.

    Thanks in advance

    Regards

    Ujjwal

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • AHB wait state insertion

    rajaraman r
    rajaraman r

      1.In AHB except a single transfer inset a wait state in middle of the burst only or insert anywhere in a burst.

      2. In INCR burst transfer can i insert a BUSY in a middle of the burst or must insert a last of the burst.

    • over 2 years ago
    • System
    • SoC Design forum
  • AMBA AHB

    vinod474
    vinod474

    Hi,

    Can any one explain me how address decoding is done in amba ahb?

    • over 2 years ago
    • System
    • SoC Design forum
  • HRESP

    vinod474
    vinod474

    HRESP  is given  for address or data??

    • over 2 years ago
    • System
    • SoC Design forum
  • amba ahb

    vinod474
    vinod474

    hi,

    Is HREADY is used by the slave  to notify the master that it is ready to receive or to indicate transfer is completed??

    thanks in advance

    • over 2 years ago
    • System
    • SoC Design forum
  • Relation between Hsel and Hready in AMBA AHB

    Purva
    Purva

    Hi,

    In my design I am having a scenario where my Hsel goes low during the data phase of a transfer and Hready goes high one cycle after that? (i.e hready high during address phase low during data phase and high again in the follwoing cycle 1->0 -> 1)…

    • over 2 years ago
    • System
    • SoC Design forum
  • AHB_LITE Extended address phase

    Muthuvenkatesh
    Muthuvenkatesh

    Hi All ,

                          The following figure shows the INCR4 burst transaction.

    Here the address increment is happening in each clk cycle  As per AHB protocol Single outstanding address is allowed.

    What are the possible adjustment has to be made for this transaction…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • Error scenario in AHB protocol

    VijeyShankar
    VijeyShankar

    Hi,

     I am developing a RTL code for AHB lite - AXI bridge. I want to understand what are the possible error scenarios in AHB?

    1.I can think of invalid address as the only case. Is there any other scenario?

    2. I am performing a INCR4 transfer on AHB side…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • Alignment Address Calculation in AHB

    Aman007kc
    Aman007kc

    Hello I want to know the calculation for

    HSIZE=2 and Wrap 8

    and starting address is 0x4

    and how we are doing alignment ???

    • over 1 year ago
    • System
    • SoC Design forum
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