• AXI4 Burst Transactions

    surajrgupta
    surajrgupta

    I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction.

    Eg. Burst length- Two , Burst size 16 bytes.

    Please give me answers for different types of data bus width say for bus width …

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • AXI ARID AWID

    Vasu
    Vasu

    What is the size of AWID and ARIDs? On what basis size is determined? How the AxIDs are generated?

    • over 2 years ago
    • System
    • SoC Design forum
  • AMBA AHB5 to AHB lite

    Pavan_M
    Pavan_M

    Hello,

     what are the additional features added or removed in AHB lite;

    regards

    Pavan

    • over 2 years ago
    • System
    • SoC Design forum
  • Working frequency on AMBA- APB,AHB, AXI

    Ujjwal.K64
    Ujjwal.K64

    Hii,

    Greetings !!

    I would like to know the standard operating clock frequency and data rate of AMBA- apb, ahb, axi.

    Please someone help me out.

    Thanks in advance

    Regards

    Ujjwal

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • AHB slave

    VT
    VT

    1.) In AHB, When early burst termination is occurred, HRESP should be OKAY and HREADY should be high?

    2.) Is there any possibilities that if write transaction is in progress and if burst is not completed then HWRITE will be low after some clock. i.e. if…

    • Answered
    • over 5 years ago
    • System
    • SoC Design forum
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