• Bus Matrix

    Felix Varghese
    Felix Varghese
    Note: This was originally posted on 28th January 2009 at http://forums.arm.com

    What exactly is a bus matrix? I came across the term in ARM cortex M3 specs but couldnt find any proper description. Can someone help?
    • over 7 years ago
    • System
    • SoC Design forum
  • PL031 verilog generation

    nicolan nicolan
    nicolan nicolan
    Note: This was originally posted on 19th February 2009 at http://forums.arm.com

    Pls, I need an answer to a blocking issue  :rolleyes:

    I tried to generate a verilog code for PL031 connection matrix 2x3.
    Unfortunely generated HSEL signal for each slave doesn't…
    • over 7 years ago
    • System
    • SoC Design forum
  • the usage of WSTRB signal

    Dong Luo
    Dong Luo
    Note: This was originally posted on 26th February 2009 at http://forums.arm.com

    Hi All,
    I was going through the AMBA AXI specs, but I have some questions about the usage of the WSTRB signal. In the middle of a burst, can some bits of WSTRB be low? Again…
    • over 7 years ago
    • System
    • SoC Design forum
  • ARM Cortex ICode, DCode, System buses

    Felix Varghese
    Felix Varghese
    Note: This was originally posted on 26th February 2009 at http://forums.arm.com

    I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?
    …
    • over 7 years ago
    • System
    • SoC Design forum
  • Write Data Interleaving - AXI

    Amaresh Chaligeri
    Amaresh Chaligeri
    Note: This was originally posted on 19th March 2009 at http://forums.arm.com

    Hello,

    Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec.
    [Chapter 8.5  Write data interleaving]

    "The order…
    • over 7 years ago
    • System
    • SoC Design forum
  • In AMBA AHB, is hgrnat must be low after 1st clock cycle of an ERROR response?

    Koteswara Rao P
    Koteswara Rao P

    Hi,

    In AMBA AHB:-

         For two clock cycle SPLIT or RETRY response, hgrant must be low after 1st clock cycle of SPLIT or RETRY response.

       q)  For two clock cycle ERROR response, is it mandatory of hgrant must be low after 1st clock…

    • Answered
    • over 4 years ago
    • System
    • SoC Design forum
  • AHB HREADY low not after address phase

    Moish
    Moish

    What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles.

    Thanks

    • Answered
    • over 4 years ago
    • System
    • SoC Design forum
  • In AHB 2.0 Standard, Can I insert BUSY cycles in INCR16 burst or WRAP16 burst?

    WONG CHENG YEE
    WONG CHENG YEE

    I am a Digital Verification Design Engineer.

    Currently, I am in the process of developing an UVM Test Bench for AHB 2.0.


    I have following questions.

    1) From AHB Master side, Can BUSY cycles be inserted in middle of INCR16 burst?

    2) From AHB Master side,…

    • over 4 years ago
    • System
    • SoC Design forum
  • Why the address boundary for AHB burst should not cross 1KB

    Mohankumar
    Mohankumar

    Why the address boundary for AHB burst should not cross 1KB??

    And in case of burst operation, is that every beat the address increment taken care by master?

    • over 4 years ago
    • System
    • SoC Design forum
  • STM(System Trace Macrocell)

    dudu8
    dudu8

    Can i observe the 1KB data that it is written over the STM AXI interface from STM ATB BUS ?

    what i mean is that i want to send a 1KB data from STM AXI and observe it from the STM ATB with MIPI STPv2 format.

    • over 4 years ago
    • System
    • SoC Design forum
  • Regarding retry response

    VIJAY KUMAR
    VIJAY KUMAR

    Im new to the ahb protocol can  any on give me an idea about retry response, when a retry response is generated from slave side.

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • Burst termination with BUSY transfer on AHB

    Hyunkyu
    Hyunkyu

    I heard that when HTRANS is BUSY, undefined length burst (INCR) will be terminated.

    But when I read a document, I saw an example that BUSY transfer followed by SEQ transfer during an undefined length burst.

    Doesn't it mean that INCR is not terminated?

    …
    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • AHB revisions from AHB3 to AHB5

    Hyunkyu
    Hyunkyu

    I noticed that "Multi slave select" is one of the new features in AHB5.

    But, isn't it possible to set multiple slaves in a system with a decoder and a multiplexor?

    I think we can do that with AHB3.

    What is the major difference between AHB3…

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • AMBA

    vish9746
    vish9746

    How is it possible for AMBA bus protocol to communicate between ASB bus and APB bus,if they operate in different frequency's? ASB is high performance high frequency bus and APB is low performance low frequency bus..how that communication is happening…

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • APB3 Slave responding when PSEL = 0

    vshankar11
    vshankar11

    Hello All,

    Here at IP Level verification we have no issues as the Master APB does not latch the PREADY, but at SOC Level with multiple APB Slaves 

    The Master performs some transaction with APB SLAVE 1 and before switching to APB SLAVE 2 , it disables the…

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • AXI3 write data interleaving with same AWID

    mveereshm622
    mveereshm622

    This is regarding the AXI3 write data interleaving. I understand how the write data interleaving works when AWID=WID when a slave is accessed by multi masters or a single master which can generate multiple outstanding transactions. But I have a query on…

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • Axi4 Write Transaction

    SelvamThangam
    SelvamThangam

    I got a doubt,Does Master should wait for Bresp to send next Write transaction or it can continuously send the transaction independent for Bresp.

    • over 1 year ago
    • System
    • SoC Design forum
  • Assertion for Multiple Transfer on APB Bus

    Rakesh Venkatesan
    Rakesh Venkatesan

    Hi,

       Can you please help me in writing assertions to take care on multiple transfer in APB bus?

    Thanks,

    Rakesh

    • over 1 year ago
    • System
    • SoC Design forum
  • Amba Adaptive Traffic Profiles question

    armchronos
    armchronos

    Hi,

    I see the Amba Adaptive Traffic Profiles blog and it's interesting.

    Is it only a specification ?

    Any public domain source code (C++ or Python) or executable to generate the traffic patterns in a commercial simulator ? 

    Thanks,

    David

    • over 1 year ago
    • System
    • SoC Design forum
  • ACE protocol : Eviction and snoop request at same time

    Chakri Myneni
    Chakri Myneni

    How to handle below scenario ?

    • At time t1 let us suppose L1 data cache is evicting a line and write address is sent on write address channel by asserting AWVALID (AWREADY is high)
    • At same time t1, there is a snoop request from interconnect on snoop address…
    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • SRAM for Cortex M0 -- Does It Need to Support Byte write?

    Ming
    Ming

    For the SRAM with Cortex M0, does it need to support byte write?

    What restrictions do I have with Cortex M0 if the SRAM only support 32-bit write?

    • over 6 years ago
    • System
    • SoC Design forum
  • How can I get IP-XACT descriptions of CMSDK components?

    Steven Dennis
    Steven Dennis

    We use IP-XACT based automation tools, mainly for register views, so need IP-XACT description of the APB registers for the CMSDK components.

    • Answered
    • over 5 years ago
    • System
    • SoC Design forum
  • AHB Slave HREADY

    VT
    VT

    Hello

    I am new to AMBA and I am writing code AHB slave in one of my project, I have read specs.

    My question is Is there any specific condition for slave when it gives HREADY low?

    I am confused with HREADY signal that it is provided by the slave but at which…

    • Answered
    • over 5 years ago
    • System
    • SoC Design forum
  • AHB

    VT
    VT

    Hello,

    1.) Is it possible in real system that Master will send start address 0x01 ?

    If Master wants to write only one byte at address 'h1, other addresses what ever value it has then how Master will give request?

    HADDR=32'h1, HSIZE=0, HWRITE=1, HBURST…

    • Answered
    • over 5 years ago
    • System
    • SoC Design forum
  • Partial Word Access to Altera Avalon Memory-Mapped Slave

    Qiangsheng Xiang
    Qiangsheng Xiang

    when I say partial word access, I mean 16-bit (two byte) or 8-bit (byte) read/write.

    Background:

    In one of our recent projects, Cyclone V SoC is used to replace 386 CPU in an existing product.

    I am responsible for the board and FPGA design. Another software…

    • Answered
    • over 4 years ago
    • System
    • SoC Design forum
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