• Error in AMBA 5 CHI spec?

    David Zuo
    David Zuo

    P189, 5.2.1 Dataless transaction without memory update

    Why does RN-F0 transition I->UC, rather than UCE or UD? After MakeUnique, RN-F0 has obtained the right to modify the cache line by discarding all other copies, dirty or not, in other caches. The purpose…

    • over 2 years ago
    • System
    • SoC Design forum
  • Where to find CHI protocol checkers and CHI testbench ?

    armchronos
    armchronos

    Hi,

    I'm trying to build an IP to interface to CHI.

    Where to download CHI protocol interface checkers (written in SVA) ?

    Where to find a CHI testbench to stimulate the various CHI related interfaces : SN_F_I, RN_I, RN_D_F (Slave Node fully coherent…

    • over 2 years ago
    • System
    • SoC Design forum
  • AXI-lite tlast signal missing and tready behavioral

    hayk
    hayk

    Dear Forum,

    Can someone please clarify my 2 questions:

    a)

    Why in AXI lite protocol there is no tlast port?

    Mainly AXI lite consists of AXI-stream protocols, but there is no tlast port in AXI lite. Can someone justify what was the reason of not including…

    • over 2 years ago
    • System
    • SoC Design forum
  • Hazard conditions in CHI

    David Zuo
    David Zuo

    In chapter 4.9.2 At the ICN(HN-F) node CHI specification talks about what ICN should do when there is hazard condition. It says:

    One example of these rules is chapter 5.6.1 CopyBack-Snoop hazard at RN-F, Figure 5-22 CopyBack-Snoop hazard at RN-F exa…

    • over 2 years ago
    • System
    • SoC Design forum
  • AXI AHB APB quick reference cheat sheet

    MattHutson
    MattHutson

    Hi,

     I have tried to find a quick reference for AXI, AHB & APB to no avail, and after having to flit between the various documents and tables, I eventually created my own.

    So not sure of the legal ramifications of posting this elsewhere and whether…

    • over 2 years ago
    • System
    • SoC Design forum
  • How to understand Exclusive Transaction failure conditions in CHI?

    David Zuo
    David Zuo

    The purpose of Exclusive Access is to read, calculate and modify a cache line atomically. The built-in Atomic Transactions can do some basic calculations at ICN or SN, but if more complex operations are necessary, Exclusive Access is needed.

    CHI specification…

    • over 2 years ago
    • System
    • SoC Design forum
  • AHB protocol

    parimita
    parimita

    I am newly learning AHBprotocol  i just want to know what is meaning of single cycle bus master handover?

    • over 2 years ago
    • System
    • SoC Design forum
  • Additional Control Information Questions

    Dalas Yoo
    Dalas Yoo

    Hi. I recently got the ARM AMBA specification in my work, and now I am learning stuffs. But the Additional control information got me stuck for a day haha

    My questions are

    1. What is the reason to use the Cacheable bit in the Cache support? I wish I…

    • Answered
    • over 2 years ago
    • System
    • SoC Design forum
  • CHI/ ACE-Lite Interface

    Sidhaarth
    Sidhaarth

    I have a custom accelerator to be integrated with Corelink CMN-600. The CMN-600 has a CHI/ ACE-Lite Interface. How can I add a CHI/ ACE-Lite Interface to my custom accelerator? Is there a tool which can generate the RTL for CHI/ ACE-Lite?

    • over 2 years ago
    • System
    • SoC Design forum
  • AMBA AXI reset

    Sreekanth Reddy
    Sreekanth Reddy

    According to spec IHI0022D_amba_axi_protocol_spec  section A2.1 page number: A2-28

            "All signals are sampled on the rising edge of the global clock "

         Q) Should RESET_N also  be sampled on the rising edge only?

    Section A3.1.2,  says

       "The AXI protocol…

    • over 2 years ago
    • System
    • SoC Design forum
  • apb 2.0 continuous transfer

    rajaraman r
    rajaraman r

    Hi All,

          Now i am focusing on the apb 2.0 specification. 

         How to perform a continuous transfer in apb 2.0 . I read some forum , But i did't get a idea.

          If anyone know the continuous transfer in apb 2.0 ,Please share the waveform . It;s easily…

    • over 1 year ago
    • System
    • SoC Design forum
  • apb protocol checker (assertions)

    kmk
    kmk

    How can I get apb protocol assertions on arm official site? Thanks in advance, KMK

    • over 1 year ago
    • System
    • SoC Design forum
  • why PSTRB signal in APB4 have four bits?

    anshu
    anshu

    PSTRB signal indicates which byte lanes to update during a write transfer.

    it shows that the bus contain valid data, when PSTRB[3:0]=1111.

    why we need bus instead of single bit PSTRB signal?

    • Answered
    • over 1 year ago
    • System
    • SoC Design forum
  • Can the ARM corrupt the timing on the AXI bus

    skbrown
    skbrown

    I have a Cyclone V SOC system, and the ARM is running Linux, and the FPGA is running SDI video and VIP suite items. The FPGA DDR memory is being used by the VIP suite and all works well. The ARM is using the DDR memory attached to it, and Linux does not…

    • over 1 year ago
    • System
    • SoC Design forum
  • Why does AHB or APB support only 16 slave devices?

    Ravindran
    Ravindran

    I would like to know why only 16 slave device select lines are present in the AHB and APB bus architectures.

    • Answered
    • over 4 years ago
    • System
    • SoC Design forum
  • what are these axi transaction types mean? fixed, incremental, wrapped, reversed? Are there any docs descriped them in detail?

    bander
    bander

    As the title says..

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • AXI

    Muthuvenkatesh
    Muthuvenkatesh

    What is byte lane in AXI?

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • read transfers

    vidya
    vidya

    In read transfres how the slave indicates the transaction is over?

    • over 3 years ago
    • System
    • SoC Design forum
  • AXI read transfer

    vidya
    vidya

    If the slave is not able to process read request from master, which response is expected from slave?

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • AXI

    Muthuvenkatesh
    Muthuvenkatesh

    Why burst must not cross 4kb  in AXI ?

    • over 3 years ago
    • System
    • SoC Design forum
  • axi read transfers

    vidya
    vidya

    what is the difference between overlapping and out of order transfers in Aciform the explanation it seems that both are same is this the case?

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • 4k boundary in AXI

    vidya
    vidya

    Why the word boundary in AXI is 4k?

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • AXI transfer

    isounder
    isounder

    Consider Data interface is 64 bit.
    It is Write transfer.
    AXI master need to transfer 11 bytes and starting address is 0. Anyone suggest which one is a valid among below mentioned two scenarios.

    Scenario 1:
    Burst -> Address:0, size:3, length:1, burst_type…

    • Answered
    • over 3 years ago
    • System
    • SoC Design forum
  • AHB wait state insertion

    rajaraman r
    rajaraman r

      1.In AHB except a single transfer inset a wait state in middle of the burst only or insert anywhere in a burst.

      2. In INCR burst transfer can i insert a BUSY in a middle of the burst or must insert a last of the burst.

    • over 3 years ago
    • System
    • SoC Design forum
  • Why do AMBA AXI does not support AxBURST of decrementing address type?

    rssortur
    rssortur

    Use case which come to my mind is.

    1. Display controller might need to flip an image 180 degrees. Here memory reading pattern is reversed.

    2. Where ever there is LIFO (Last In Fist Out) implementations.

    • over 3 years ago
    • System
    • SoC Design forum
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