How to handle below scenario ?

• At time t1 let us suppose L1 data cache is evicting a line and write address is sent on write address channel by asserting AWVALID (AWREADY is high)
• At same time t1, there is a snoop request from interconnect on snoop address…

Hi,

From hardware perspective, what's the purpose of WACK and RACK and how does it affect the ACE protocol ?

I can see that the specification says the master issues these two signals to indicate to the interconnect that Write and Read transactions…

Hi,

The AMBA5 spec for ACE5 shows some new signals versus ACE4 :

VAWQOSACCEPT

VARQOSACCEPT

AWAKEUP

ACWAKEUP

SYSCOREQ

SYSCOACK

How are these used in an SOC system ?

For example, I think but I'm not usre if VAWQOSACCEPT, VARQOSACCEPT is output by each slave…

Hi ARM/arktos,

Seems like this online discussion is not working properly.

I ask a question, you reply, and if I reply the discussion tool doesn't echo back my reply by email.

So most likely you may not see it.

Below is my reply to your answer to my…

Hi,

1) ARBAR/AWBAR

These two signals are mentioned : ARBAR, AWBAR but in the AMBA5 spec F2.1 Signal Matrix, these signals are listed as "N" (must not be present), page 419 and 420 of 440 pages. 

So are these signals used on the ACE5 interface…

If the slave is not able to process read request from master, which response is expected from slave?