In my little program (rpi_stub) it's time to turn on MMU and caches.
Most of it I seem to have hold of, except cache invalidations.
In multicore situation (rpi_doesn't support yet, but maybe later), what needs to be invalidated and how?
I understand…
Hi All!
I am working with a Xilinx Zynq 7000 SoC which uses the Cortex A9 as a CPU.
I've observed a problem wherein a section of memory marked strongly-ordered and non-cacheable (0xc02) in the MMU table gets corrupted by what appears to be L1 evictions…
i am not able to understand working of this CACHE signal pleas explain with simple example.
thank you!
Hi,
I am reading ACE protocol and i am confused about when to use cache maintenance transactions. On what basis should i decide when to use cache maintenance transaction and which transaction to be used?
Can anyone please help?
Hi,
I want to know which transaction should be issued by ACE interface on the channel when a flush/clean request is being processed by the cache?
Can anyone please help.
Regards,
Taniya Garg
Hi everyone,
I'm currently working on type-1 hypervisor and would like to provide support of the ARM Power State Coordination Interface. http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D…
