Hi all,

I am new to protocols AHB and AXI.

can anyone explain why there is 4kb boundary in AXI and why there is 1 kb boundary in AHB?

Also what these boundaries are for? Does they represent the maximum slave size?

I have three question on AXI transfers, and these all relate to
a) my understanding of the spec, as all question do, and
b) a single write transfer to a single 32-bit aligned address.

I would like to make a single transfer to write only byte 2 at address…

Hi, I am not so clear about the concept of transfer size in AMBA AXI. My question is how to calculate wrap_boundary in wrap based data transfer when Number_Bytes (The maximum number of bytes in each data transfer) is changing in each transfer within a…

Hii,

In AXI 3 if  data items are written before the address comes due to register delays .....then where that data is being stored in memory because no address is being specified till now...?

please resolve this issue...

Thanks 

In AXI4 Stream protocol apart from data byte two other byte types are defined known as position byte and null byte. 

For the position byte the description says: "A byte that indicates the relative positions of data bytes within the stream. This is a placeholder…

Hello I am  new to AXI and just saw the pseudocode for a transfer in the spec of AXI . My question is regarding Data_Bus_Bytes .

Q1-  The spec says that Data_Bus_Bytes is  number of 8 bit byte lanes in the bus. Is it same  as Number_Bytes which is 2^AWSIZE…

Can somebody please explain how barrier transactions in ACE work?

Thanks in advance.

A master wants to initiate write transfers to two different slaves whose address ranges are consequtive   can he choose to initiate write transfer starting in 1st slave address range and choose ASIZE and ALEN such that second slave is also covered? if yes…

Hello,

I am unable to understand , which start address should i take in case of wrapping burst address calculation of AXI?

For example , 

my Burst size=4 transfers(beats)

each beat(transfer)size=4bytes=32bits.

hence total size of burst=32*8=256bits. Hence…

Hi,

We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data RAM with the bits found in the tag RAM. For example,…

Hi,

In the AXI spec it is mentioned that , even in case of ERROR response, the slave needs to respond with the exact number of beats and indicate the response with each beat.

Now my question here is if the response is going to be ERROR(lets say SLVERR…

Hi,

In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate.

But is there any concrete reason for this change? Actually I found some related statements from spec, but I couldn…

In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under "Store operations where the cache line is already cached" as :

The initiating master component requests a unique copy of the cache line…

Hi ,

   What is the purpose of removing ID's (WID) in AXI4 ?

If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please tell me if any other reasons...(Arm Spec says.…

Hi,

In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions.

My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted that "Dependencies on the assertion of WVALID also require…

Hello everyone,

I'm pretty new to axi and i still try to figure things out. I'm using Zybo device and created a custom ip with a master and a slave interfaces. I have create design as you can see in the below. Write transaction is work however, read transaction…

i am not able to understand working of this CACHE signal pleas explain with simple example.

thank you!

Hi,

I am verifying a low complexity RTL design having AX Iinterface. I am working on this AXI master connected with AXI VIP slave interface. I see that in a few scenarios, when AXI master timesout, the WLAST signal is not generated  at the master interface…