Hi,

Can someone clarify below queries I have wrt AHB-Lite,

1. Is there any relation between HTRANS=IDLE and hready ? Like,
   1. Whenever IDLE comes hready is de-asserted (or)
   2. Whenever hready is de-asserted, master gives IDLE
2. What is the maximum duration…

HI...

A)

     1). I am now using a continuously 10 transfer of the SINGLE BURST write based read transfer. In spec says the default ready signal is HIGH.

     2).First thing i complete the first transfer of the write based read operation.

    3). Then it takes…

HI 

     I am using a single transfer in ahb lite in wait state.First i am write till htrans will maintain or not.

    If i am using a write based read ,The write is not complete due to wait at the time ,At the time again i put a same addr in read transfer…

Hi All,

               Consider the following burst transfers.

1. INCR4 (WR) IDLE INCR4(RD)

2. INCR4 (WR) INCR4(RD)

3. INCR4 (WR - WR1 ,WR2, IDLE, WR3 ,WR4 )   INCR4(RD)

             All the above transactions are valid transfer or not .

Can we trigger multiple burst…

Hello to all,

I have a question about AMBA3 AHB-Lite and AHB5 Specification:

In AMBA3 AHB-Lite Specification, "Table 6-2 Active byte lanes for a 32-bit big-endian data bus" is mean word-invariant big-endian or byte-invariant big-endian? Why its…

Hello to all AHB experts,

I have some question about AHB-Lite interconnection.

If I want to build 2 masters share 1 slave systems. I add a arbiter in the interconnect circuit, so that only one master could access the slave at a time.

My question is how…