Hi,

Can someone clarify below queries I have wrt AHB-Lite,

1. Is there any relation between HTRANS=IDLE and hready ? Like,
   1. Whenever IDLE comes hready is de-asserted (or)
   2. Whenever hready is de-asserted, master gives IDLE
2. What is the maximum duration…

Hello,

i didnt find at spec any note about the waited write transfer.

for example 

T1 : NONSEQ + write transfer  + HREADY is high

T2: HREADY dropped + HTRANS is idle - HWDATA ?

does the HWDATA have to be the right data or it can be any junk ? and only when…

Hi all,

I am new to protocols AHB and AXI.

can anyone explain why there is 4kb boundary in AXI and why there is 1 kb boundary in AHB?

Also what these boundaries are for? Does they represent the maximum slave size?

Hi sir,

       T1=NON-SEQ

       T2=BUSY

       T3=SEQ

       T4=SEQ

      T5= SEQ

         This is for WRITE operation:

         i am  using a BUSY state for T2. Then my WAIT state for till T3.  I have read from the forum if WAIT state u are using a BUSY transfer, you can change next…

Hi sir,

        I am now new to AHB. In the AHB wrap4 transfer, i can use a second cycle is a busy cycle, and also i am using a WAIT state for first 4 clock .In spec says if u use a busy state then the slave provide a zero wait state. In my case i am using…

HI 

     I am using a single transfer in ahb lite in wait state.First i am write till htrans will maintain or not.

    If i am using a write based read ,The write is not complete due to wait at the time ,At the time again i put a same addr in read transfer…

The AHB starting address is only a even or odd . If odd  how to calculate the wrap boundary calculation in WRAP4 ,hsize=2.   

Regards

Rajaraman R

Hello All,

            I am using a WRAP4 burst and my HSIZE=O.

           So boundary=(beat * hsize in byte)

                               = 4 *1

                              = 4

          My starting addrss=217

          The wrap4 will increment to 217,218,219,216.

          This is correct or not

why okay response is single cycle?but error,split,retry is two cycle.why?

Hello,

We are using ARM Matrix IP that is acting as a Master and using our VIP as a slave.

ARM Matrix is sending a initiating a WRITE Transfer on a slave when HREADY is low, but not keeping control signals stable till HREADY becomes high.

So the questions…

Hi Everyone,

Consider an AHB transaction in which the AHB slave signals an error response, and the AHB master decides to continue the transfer with the present slave. Following are three waveforms that depict the AHB transfer. In all the three cases the…

Hi everyone,

I have a question regarding the data during the BUSY state in a AHB bus. Consider the following example of an AHB master writing data onto an AHB slave: