• LPC43XX (Cortex-M4): Timer triggered DMA transfer?

    Andrea Bettati
    Andrea Bettati

    Hi to you all,
    thank you for your patience: I know I'm publishing a lot of LPC43XX related questions. but the support on NXP forums is just.. well, something different from the one I found here, so I keep taking advantage of your know-how: maybe one…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex M4 (LPC4370): how do I detect ADC threshold crossing while moving data in a DMA driven double buffer?

    Andrea Bettati
    Andrea Bettati

    Hi to you all,

    I'm currently working on a project involving the LPC-Link2 as a eval. board for it's LPC4370 (for a complete explanation see this question).
    What I'm trying to do is:

    • Continuously sample external analog signal (using on-board…
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Hard Fault in cortex m4

    hemant
    hemant

    Hello All,

    Good Morning!

    I am working on Cortex m4.

    I have read following about hard fault ,

    "Bus Fault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and register stacking (save/restore) on interrupt (entry/exit…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Can we Modify the Flash Memory Access Permission with MPU( Memory Protection Unit)

    harshan
    harshan

    Hi Sir,

             Can i change Flash Memory Permission through MPU??

    Thanks and Regards,
    Harshan.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Loss of information - SMMUL

    Petr
    Petr

    Why the Cortex M4 instruction SMMUL (32 = 32 x 32b) preserves a redundant sign bit and discards one useful bit of information? What could possibly be the justification for such blatant disregard of the ISO/IEC TR 18037 standard Fract format?

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Snake robot with ARM Cortex-M4 processor

    Prashant.Sulakhe
    Prashant.Sulakhe

    I want to design an snake robot with ARM Cortex-M4 processor can u help how to start? please help me.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Enabling NEON Instructions on Pixhawk

    Nathan Szanto
    Nathan Szanto

    I am trying to get a quadcopter flying using the Pixhawk controller (Cortex M4 running NuttX RTOS) and I am using the Simulink Pixhawk PSP to implement a custom controller. Our controller uses neural networks, so neon instructions are needed (the build…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to get absolute value of a 32-bit signed integer as fast as possible?

    Matic
    Matic

    Hi.

    I wonder how to calculate absolute value of a 32-bit signed integer in C as fast as possible. I saw that there is a FPU instruction VABS.F32, which do that in one cycle (above the floats). I thought, if it is possible to use it also with integers …

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • DSP instruction for x*x + y*y. Does it exist?

    Matic
    Matic

    Hello all!

    I am new to ARM community and this is my first question here. I work on embedded systems where we use Cortex-M4 based MCUs (concretely STM32F3 series). I would like to ask, if there is a DSP instruction which would calculate x*x + y*y.

    x and…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • What is the meaning of a 64 bit aligned stack pointer address?

    Murtuza Quaizar
    Murtuza Quaizar

    According to ARM Architecture Procedure Call Standard (AAPCS) on the ARMv6-M, and ARMv7-M architecture in  it says:

    "Although the processor hardware allows SP to be at any word aligned address at function boundaries, standard programming practice…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • PSP Stack Pointer, what memory address does it point to?

    Murtuza Quaizar
    Murtuza Quaizar

    In the ARM Cortex M4, If the PSP stack pointer is configured, what address space does it point to?  Is it the same address space as the MSP (main stack pointer)? Or do we create a new and separate stack for it?  And how do we configure the TOP of stack…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • wfi in debug mode

    sandeep
    sandeep

    Hi,

    Please help me understand expected behavior of CM4 when CM4 is in debug mode and WFI is executed through single step.

    Does CM4 enter sleep/sleepdeep in such case ?

    Thanks,

    Sandeep

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Problem: WFI instruction slowing down SYStick interrupt

    Saqib Ahmed
    Saqib Ahmed

    I've configured my Infineon relax kit for max frequency(120 MHz). I've set my SYSTick for a periodic interrupt of 10 ms. For power saving, I use a WFI assembler instruction whenever my processor is idle. WFI (wait for interrupt) should put the processor…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • clock configuration of xmc4100

    harshan
    harshan

    Greetings,

                   sir/madam i am working on xmc4100 after reading the reference manual i am tried to configure the clock (CCU) which was present under system control unit (SCU…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • M4  M7 COMPARISION

    Varatharajan
    Varatharajan

    Hi Folks,

    Can you share some little information about Pro/Cons of ARM Cortex M7 towards current variance ARM Cortex M4?. I just screen that M7 has 6 deptth pipeline for instruction and it is best suit for DSP with high performance

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Problem in copying functions to RAM on ARM Cortex-M

    Freddie Chopin
    Freddie Chopin

    I'm (again) facing a very strange problem in my project for ARM Cortex-M4 (STM32F301K8). The project requires some of the functions to be executed from RAM (it's actually a bootloader with encryption and option to self-update, but that doesn't matter…

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to acknowledge/clear active interrupt in Cortex-M4

    Deepak Jharodia
    Deepak Jharodia

    Hi all,

    I'm testing interrupt on a Cortex-M4 based platform. So far I have managed to get my interrupt handler called. It clears the interrupt source coming from the peripheral. But before the pin to NVIC is de-asserted, the handler is called again. At…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Get current active interrupt priority

    Jonathan Weber
    Jonathan Weber

    Hi everybody,

    We are working on a simple priority RTC (run to completion) framework for the Cortex M3/M4. Thanks to the NVIC/BASEPRI, we got most of this functionality for free but we want to extend it to user tasks.

    In our implementation we need to determine…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • 'Sort and Count' program using Cortex-M3 Assembly (or less preferably in C language)

    Vickey Khan
    Vickey Khan

    Construct the following null terminated string in code area (i. e. in ROM)

    str         DCB       “p1er3fec6tst1r2an5ge7rs8”.0

    Write an assembly program that will count and…

    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Break Points and Watch Points

    harshan
    harshan

    Greetings,

                   Sir,i am working on SWD, after  Research on Break Point & Watch Point i found One Thing That There are Some Comparators will Do These Things but I am not Very Sure That How These are Work …

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • [C++11][Cortex-M] - distortos - object-oriented C++ RTOS for microcontrollers

    Freddie Chopin
    Freddie Chopin

    Hello!

    I finally decided to share some info about a project I've been doing for the past 8 months. Currently it can be considered "alpha" or maybe "early beta" stage, but - despite literal meaning of these terms - the things that are already done (and…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Question about application of PendSV

    Gopal Amlekar
    Gopal Amlekar

    Reading jyiu book on Cortex-M4 and general information about usage of PendSV exception type.

    One application highlighted is of context switching in the RTOS wherein on a Systick timer interrupt, instead of context switching, it will set the PendSV bit…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • What is better as mutex on Cortex-M4 - Bitband or LDREX/STREX

    Amir
    Amir

    The two options are available.

    What is the difference in respect of "cost" "speed" and "complexity" for the two method?

    When we need more than few mutexs like that, say 100, is the answer different?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Current priority level of processor

    Gopal Amlekar
    Gopal Amlekar

    Hi,

    I have been reading about the exception mechanism of Cortex-M (M4 to be precise). The exception request is accepted by the processor if the current priority level of the processor is less than the incoming exception (this is one of the conditions to…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Problems with interrupting LDM/STM Cortex M4?

    Paul Giangrossi
    Paul Giangrossi

    I am seeing stack corruption running a Cortex M4 that seems to be related to interrupting multicycle instructions.

    The interrupt occurs during a STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr}

    The ICI bits at the time of the interrupt equal 7. This means that…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
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