• Is there any relationship between BOOT and REMAP in design kit?

    ele
    ele

    Hi Now I'm trying to digging the design kit.

    But I cant' find the BOOT relative port or signal and REMAP signal in the design kit.

    As I know usually BOOT used such as the following picture

    But I can't find any relative interface in the design…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • LPC1768 Interfacing with USB HDD

    hmesut
    hmesut

    I want to Interfacing LPC1768 with 1TB External USB Hard Disk

    Can LPC1768 support it?

    I don't know how do it

    please help me . i really need it and it's very important

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • mismatch between ARMv7-M ref manual and core_cm7.h

    jheissjr
    jheissjr

    The ARMv7-M reference manual notes there eight ITM trace enable registers called ITM_TER0 to ITM_TER7.  However, core_cm7.h only has one ITM_TER register.  Can you clarify?  Is it an error in core_cm7.h?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Processor sometimes ignoring WFI instruction

    Adrian
    Adrian

    Hello everyone,

    I have a problem with WFI instruction and deep sleep mode.
    Normally everything work correct, but sometimes processor ignore instruction WFI and continue work.

    I use ARM Cortex-M0+ (exactly STM32L051), and below is my sleep procedure:

    	__ASM…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • What happens if a same priority exception came while context-switch is executing?

    kaizsv
    kaizsv

    Hello, I meet a problem while using Spin Model Checker to verify a RTOS kernel based on Cortex-m3 platform.

    My PendSV is in the lowest priority 16 and perform to schedule next user task and context switch. While PendSV is executing, another exception…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • What happens when offset value becomes 30 in case of load/store operation

    HimanshuDoshi19
    HimanshuDoshi19

    Hello to all,

    I was looking at different offset values for both load and store operations. Since due to little endian arrangement, the memory looks something like this to processor:

    Byte[0x23],Byte[0x22],Byte[0x21],Byte[0x20]

    Byte[0x1F],Byte[0x1E],Byte…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How can I test uSDCARD of V2M-MPS2 board?

    jchou_1992
    jchou_1992

    Hello:

    I'm going to test uSDCARD read/program function via external SPI connector of MPS2 board. 

    Can you please tell me where I can download the test code and documents? 

    Thanks

    Jimmy 

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Learning lpcxpresso

    KUMA
    KUMA

    Hi friends I am new to lpcxpresso. I have lpc1769 kit and I am thinking of buying books on arm cortex m3 to get familiar with it. Is it worth? If then how much is it helpful? Additionally I was thinking of watching videos of cortex m3 programming that…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to start Firmware separated in I-RAM and D-RAM within Cortex-M3 design kit?

    ele
    ele

    Hello?

    I'm trying to implement the Firmware with the Cortex-M3 SoC which is separately designed I-RAM and D-RAM  in Keil MDK.

    As you can see the above example system, AHB Interconnect have 3 slaves S0, S1 and S2. and S0 and S1 are connected with…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Using GPIO for timing execution of functions

    w1res
    w1res

    I have a need to measure the execution time of certain functions using an oscilloscope. When I enter the function I toggle a pin high, and before exiting the function I toggle the pin low.

    I'm using an STM32F7 (Cortex M7) processor and using armcc in…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Fail to add JTAG/swd debug into Cortex-M0

    sieg70
    sieg70

    Hi,

    I have been trying to add the debug function into my Cortex-M0 design for FPGA implementation targeting at Xilinx Spartan-6.

    Both JTAG or SWD are failed to work although the cortex-m0 seem function well (it execute the code and make LED blinky).

    What…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How do I implement the cortex M3 Boot ROM code?

    ele
    ele

    Dear All,
    As I know, In Cortex M3, was implemented such as the B_ROM, I_RAM, D_RAM .
    and Basically, Cortex M3 is consist with internal memory ROM and SRAM.
    In Boot sequence, first of all, IROM code load BL1 code into the SRAM.
    So I want to know especially…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Interrupt switching during Late Arrival- CortexM3

    Vartika Singh
    Vartika Singh

    In Cortex-M3 manual, it is mentioned that during Late Arrival, when low-priority interrupt (LP) has already pushed 8 registers to Stack and high-priority interrupt (HP)occurs then, for (HP), we don't need to do any state saving. What does it mean by …

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to start accessing the flash rom on Cortex-M3 design kit by JTAG?

    ele
    ele

    Hi,

    I'm trying to simulate which is accessing the flash rom on Cortex m3 design kit by JTAG?

    Is there any related test case or example?

    How to start accessing the flash rom on Cortex-M3 design kit by JTAG?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • MPU is not triggering MemFault or HardFault

    Muzahir
    Muzahir

    MPU is not triggering MemManage fault. I want to protect a memory region of 64 bytes starting from 0x20000000. I've configured the MPU registers accordingly, but when I write in a protected memory location, MPU does not trigger fault.

    Here's a code…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to implement to write firmware by JTAG within CM3 design kit?

    ele
    ele
    • Dear all,  

    I believe that you know such as STM32F103 cpu series support firmware program function by using JTAG with JTAG debugger of keil MDK.

    So I want to know does cortexm3 design kit include such as  JTAG firmware program function blocks? 

    What am…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • what happens when same interrupt comes to much fast on IRQ pin of ARM926ej-s?

    nirav
    nirav

    In ARM926ej-s processor architecture there are two interrupt lines IRQ, FIQ. Suppose on IRQ line,interrupt comes too fast after one interrupt is latched. So is there any queue  which will store pending interrupt request or when the first interrupt came…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to interface TFT display with lpc1768

    chinna@422
    chinna@422

    I am new to lpc1768, i facing problem in how to start interfacing TFT mr024-9325-51p 2.4" DISPLAY . please help me in that. if anybody provide example code that will help me alot. thank you.

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • MFLOPS of M4F

    Timm Hinrichs
    Timm Hinrichs

    Hi,

    we are operating the M4F with 160MHz and we would like the know the MFLOPS we can achieve with this configuration.

    Regards,

    Timm

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Adding External E2PROM, PROM or SRAM to a basic M0 development board

    Sean Dunlevy
    Sean Dunlevy

    I'm not quite sure if this is the right place to ask the question so please forgive me if I've made a mistake.

    I am developing a variable-rate ACELP Wideband decoder for the M0. While the code and work-RAM are small, I need a lot of space to store…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Trying to find basic performance measurements of ARM cores

    eskimoalva
    eskimoalva

    Howdy, I was trying to find some basic performance benchmarks for a couple of different ARM cores: The Arm 926EJ-S, Cortex A9, and the Cortex M7.

    I am looking for primarily DMIPS (per MHz or a form that requires me scaling to my specific chip is fine…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • cortex m0

    sergio
    sergio

    I need the ARMv6-M Architecture Reference Manual and ebrising abaut the cortex m0

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Registers and Cache on M0

    Sean Dunlevy
    Sean Dunlevy

    Hi,
         Coming from a games coder background, I always seek to find the very limits of what a CPU can do. Now we have PragmatIC and very cheap CPUs but much more importantly - vastly cheaper MROM (Mask ROM). With this in mind, I wanted to know how many registers…

    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Does Cortex-M3/M4 continue with burst in response to ERROR?

    MSaif
    MSaif

    AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.
    What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M4 - Returning from Interrupt

    marcusob
    marcusob

    Hi,

    I'm using the STM32 F407 (Cortex M4), and I am also only using assembly in uVision IDE. So far I have managed to setup a ISR for a pushbutton generated interrupt via GPIO. This all works, I get the ISR handler hit, but after I perform my ISR function…

    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
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