Hi Now I'm trying to digging the design kit.
But I cant' find the BOOT relative port or signal and REMAP signal in the design kit.
As I know usually BOOT used such as the following picture

But I can't find any relative interface in the design…
Hi Now I'm trying to digging the design kit.
But I cant' find the BOOT relative port or signal and REMAP signal in the design kit.
As I know usually BOOT used such as the following picture

But I can't find any relative interface in the design…
I want to Interfacing LPC1768 with 1TB External USB Hard Disk
Can LPC1768 support it?
I don't know how do it
please help me . i really need it and it's very important
The ARMv7-M reference manual notes there eight ITM trace enable registers called ITM_TER0 to ITM_TER7. However, core_cm7.h only has one ITM_TER register. Can you clarify? Is it an error in core_cm7.h?
Hello everyone,
I have a problem with WFI instruction and deep sleep mode.
Normally everything work correct, but sometimes processor ignore instruction WFI and continue work.
I use ARM Cortex-M0+ (exactly STM32L051), and below is my sleep procedure:
__ASM…
Hello, I meet a problem while using Spin Model Checker to verify a RTOS kernel based on Cortex-m3 platform.
My PendSV is in the lowest priority 16 and perform to schedule next user task and context switch. While PendSV is executing, another exception…
Hello to all,
I was looking at different offset values for both load and store operations. Since due to little endian arrangement, the memory looks something like this to processor:
Byte[0x23],Byte[0x22],Byte[0x21],Byte[0x20]
Byte[0x1F],Byte[0x1E],Byte…
Hello:
I'm going to test uSDCARD read/program function via external SPI connector of MPS2 board.
Can you please tell me where I can download the test code and documents?
Thanks
Jimmy
Hi friends I am new to lpcxpresso. I have lpc1769 kit and I am thinking of buying books on arm cortex m3 to get familiar with it. Is it worth? If then how much is it helpful? Additionally I was thinking of watching videos of cortex m3 programming that…
Hello?
I'm trying to implement the Firmware with the Cortex-M3 SoC which is separately designed I-RAM and D-RAM in Keil MDK.

As you can see the above example system, AHB Interconnect have 3 slaves S0, S1 and S2. and S0 and S1 are connected with…
I have a need to measure the execution time of certain functions using an oscilloscope. When I enter the function I toggle a pin high, and before exiting the function I toggle the pin low.
I'm using an STM32F7 (Cortex M7) processor and using armcc in…
Hi,
I have been trying to add the debug function into my Cortex-M0 design for FPGA implementation targeting at Xilinx Spartan-6.
Both JTAG or SWD are failed to work although the cortex-m0 seem function well (it execute the code and make LED blinky).
What…
Dear All,
As I know, In Cortex M3, was implemented such as the B_ROM, I_RAM, D_RAM .
and Basically, Cortex M3 is consist with internal memory ROM and SRAM.
In Boot sequence, first of all, IROM code load BL1 code into the SRAM.
So I want to know especially…
In Cortex-M3 manual, it is mentioned that during Late Arrival, when low-priority interrupt (LP) has already pushed 8 registers to Stack and high-priority interrupt (HP)occurs then, for (HP), we don't need to do any state saving. What does it mean by …
Hi,
I'm trying to simulate which is accessing the flash rom on Cortex m3 design kit by JTAG?
Is there any related test case or example?
How to start accessing the flash rom on Cortex-M3 design kit by JTAG?
MPU is not triggering MemManage fault. I want to protect a memory region of 64 bytes starting from 0x20000000. I've configured the MPU registers accordingly, but when I write in a protected memory location, MPU does not trigger fault.
Here's a code…
I believe that you know such as STM32F103 cpu series support firmware program function by using JTAG with JTAG debugger of keil MDK.
So I want to know does cortexm3 design kit include such as JTAG firmware program function blocks?
What am…
In ARM926ej-s processor architecture there are two interrupt lines IRQ, FIQ. Suppose on IRQ line,interrupt comes too fast after one interrupt is latched. So is there any queue which will store pending interrupt request or when the first interrupt came…
I am new to lpc1768, i facing problem in how to start interfacing TFT mr024-9325-51p 2.4" DISPLAY . please help me in that. if anybody provide example code that will help me alot. thank you.
Hi,
we are operating the M4F with 160MHz and we would like the know the MFLOPS we can achieve with this configuration.
Regards,
Timm
I'm not quite sure if this is the right place to ask the question so please forgive me if I've made a mistake.
I am developing a variable-rate ACELP Wideband decoder for the M0. While the code and work-RAM are small, I need a lot of space to store…
Howdy, I was trying to find some basic performance benchmarks for a couple of different ARM cores: The Arm 926EJ-S, Cortex A9, and the Cortex M7.
I am looking for primarily DMIPS (per MHz or a form that requires me scaling to my specific chip is fine…
I need the ARMv6-M Architecture Reference Manual and ebrising abaut the cortex m0
Hi,
Coming from a games coder background, I always seek to find the very limits of what a CPU can do. Now we have PragmatIC and very cheap CPUs but much more importantly - vastly cheaper MROM (Mask ROM). With this in mind, I wanted to know how many registers…
AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.
What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?
Hi,
I'm using the STM32 F407 (Cortex M4), and I am also only using assembly in uVision IDE. So far I have managed to setup a ISR for a pushbutton generated interrupt via GPIO. This all works, I get the ISR handler hit, but after I perform my ISR function…