Hello guys,
I am trying to verify some features of ARMv7-M3 in a software simulator platform for ARM. But this simulator only support ARMv7-A ISA.
Is ARMv7-M3 instructions compatible to ARMv7-A, especially thumb instructions?
Thank you very much.
Hello guys,
I am trying to verify some features of ARMv7-M3 in a software simulator platform for ARM. But this simulator only support ARMv7-A ISA.
Is ARMv7-M3 instructions compatible to ARMv7-A, especially thumb instructions?
Thank you very much.
Hi Friends.. I am Gokhu..New to ARM..i start my learning process..i need library function of iolpc2148.h and main.h and stdio.h, RTC.h,ADC.h and DAC.h uart.h these kind of library bundle and i need a material or online site to learn arm C programming…
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Is it someway related to RTOS?, if so , how?
Hi,
As I have found in:
Cortex-M0+ Devices Generic User Guide: 2.1.3. Core registers
There is information about instruction behaviour during interrupts:
"Interruptible-restartable instructionsThe interruptible-restartable instructions are LDM, STM,…
When I read below thread in arm forum, I still not clear which one is the safety way.
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Hello All,
I am integrating CAN stack, on Spansion S6J3xx series.
I have configured Main clock as Input frequency, configured CAN transceiver IC and called CclPowerOnInit().
Now calling CanTransmit(X_TxHandle), function in a 100ms task, but still no signal…
Hi to you all,
I've another post on the forum (here's the link Process ADC data, moved by DMA, using CMSIS DSP: what's the right way? ), but since I think I made some small steps forward I felt I could be a little more specific. I hope this…
I want to design an snake robot with ARM Cortex-M4 processor can u help how to start? please help me.
Hi,
I'm looking for and ARM processor with an hardware H.264 encoder.
The production volume is 5000 boards a year.
The product will be ready in the Q1 of 2017 therefore I can evaluate also microprocessor in a preview status.
Thanks for any help,
Enrico…
Why the Cortex M4 instruction SMMUL (32 = 32 x 32b) preserves a redundant sign bit and discards one useful bit of information? What could possibly be the justification for such blatant disregard of the ISO/IEC TR 18037 standard Fract format?
Hi to you all,
I've a firmware running on a NXP LPCLink2 (LPC4370: 204 Mhz Cortex M4 MCU) board which basically does this:
Hi.
I have a question regarding Cortex-M4 processor with floating point unit. Is it somehow possible to do some computation in parallel in CPU (with integers) and FPU (with floats)?
Probably not, because both units need their own instructions to perform…
Hi Sir,
Can i change Flash Memory Permission through MPU??
Thanks and Regards,
Harshan.
in arm7tdmi, suppose instruction is being executed and at same time FIQ and IRQ both occur at same time.now according to priority FIQ will be handled then IRQ but my question is that how it will handled IRQ after return from FIQ
i means…
I could not clearly understand the alignment issues present in ARM. Sometimes I get BUS ERROR while running an assembly file but don't know how to resolve it. Some of the doubts:
1. Is it better to store registers pairwise or individually on the stack…
Core: Cortex-M4F
Do I need to configure vector table offset address to 0xnnnn_n000?
In case of 0x3080(Flash region), the program jump to unexpected code.
I think it is caused by mismatching between vector number and handler address.
In case of 0x3000(Flash…
Hi.
We are developing a product which has to achieve some safety requirements. The system is quite simple, non-OS, running in a Privileged mode only on a Cortex-M4. I would like to implement a Memory Protection Unit somehow. Could you please give any advice…
Hi.
I am writing back regarding MPU usage. I implemented it into the software in next ways (note, that program is quite simple - only privileged mode, no RTOS):
1. I enabled background region, thus all addressable memory is fully accessible, unless there…
function1 calling function2, function2 calling function3, function3 calling function4 and so on.
Maximum stage depends upon Stack Size, right? How to identify Stack Size and if required how to change it? I am using IAR and Fujitsu ARM Cortex M3 MB9AF312K…
Hello All,
Good Morning!
I am working on Cortex m4.
I have read following about hard fault ,
"Bus Fault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and register stacking (save/restore) on interrupt (entry/exit…
Dear colleagues.
I am compiling the Intel TBB in an effort to optimize my code to the Cortex-M53, however, because I was still forced to use GCC 4.9 I'm getting some warning messages about the use of 32bit Thumb Instrucions in IT blocks:
Warning…
Hi Experts,
Is there any document on general software guidelines in reducing the cache miss rate in the system for ARMV7 architectures ?
If it is more specific to A/R/M then its great..
Hi
I had a problem.
I can use vfp in user mode but not work in priviledge level.
Is there any wrong setting in CP10 , CP11 or any other wrong setting??
BR
good night everyone.
I was talking with some colleagues about Pico and Nano Satellites, as we enter the point which best microcontroller to use this type of equipment, the CubeSat team (www.cubesat.com) uses the MSP430, but the justification presented…