• Why NSCAR(Non-secure Access Control Register) changes often?

    scribnote5
    scribnote5

    Hello, experts:

    My platform has a Cortex-A9 MPCore CPU, It supports trustzone tech.

    I tried to change NSACR.TL bit, but It needs to change in the secure state.

    I checked NSACR value in non-secure state and NSACR value that I changed is changed aperiodically…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to use Secure Monitor Call(SMC) and entrance Monitor Mode?

    scribnote5
    scribnote5

    Hello, experts:

    My platform has a Cortex-A9 MPCore cpu, It supports trustzone tech.

    I want to change NSACR.TL bit, but It need in secure state.

    I want to change non-secure state to secure state by entering monitor mode using smc.

    But It is not easy to…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • dump MMU translation table for A9 in Linux

    mivascu
    mivascu

    Hello,

         I would like to know how to read the translation table info for A9  from embedded Linux.

         In freeRTOS I have translation_table.S but I do not find anything similar for ARM architecure in linux kernel.

         Should I just dump TTBR0/TTBR1 registers…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to check PTM trace from the ETB without using JTAG or other adaptor

    G1_Chang
    G1_Chang
    Hello. 
    Im using I.MX6 solox Board from NXP Cooperation.

    This I.MX6 solox has a Arm Cortex-A9 processor.

    What I am trying to do is Tracing PTM which will be stacked up in the ETB buffer. 

    I also used Zynq 7000 zc706 which has two Arm Cortex-A9 processors…
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • MMU initialization for an ARM multicore system

    ddn
    ddn

    I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib).

    On the shared SDRAM, I am planning to have dedicated memory regions for each core, and a shared…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv7 CortexA9 Cache Policy - No allocate ?

    josecm
    josecm

    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A kind of write-through / "no-allocate" policy?…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Can Floating Point Unit(FPU) in cortexA9 processor raise an exception?

    Yeli
    Yeli

    Based on  ARM documents there is no exception ID for FPU (CortexA9) and just FPU instructions set exception flags in Floating-Point Status and Control Register (FPSCR). Is there a way to use these flags to raise an exception in the processor?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Which is better of thees CPUs

    kasem
    kasem

    Which is better of thees CPUs:

    Cortex A53 octa core 1.5 ghz,

    Cortex A7 Allwinner T8 Eight core 2.0 ghz,

    Cortex A9 Quad-Core 1.8 ghz ?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ACP and DMA usage on A53

    leslielg
    leslielg

    Hi,

    I'm using DMA transfering data through ACP on A53. 

    According to A53 TRM, ACP burst size limits to 16B and 64B, does it mean the DMA connect to ACP also limited to transfer 64B data in max each time?

    Then software must re-configure DMA then re…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • MRS [A/C]PSR latency armv8-a?

    MarkL
    MarkL

    HI,

    Do anyone has a clue on the latency of the MRS CPSR (or APSR) command?

    I want to read the flags with no jump (and it is critical).

    Thanks

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Trying to find basic performance measurements of ARM cores

    eskimoalva
    eskimoalva

    Howdy, I was trying to find some basic performance benchmarks for a couple of different ARM cores: The Arm 926EJ-S, Cortex A9, and the Cortex M7.

    I am looking for primarily DMIPS (per MHz or a form that requires me scaling to my specific chip is fine…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex A9 - Enabling/Disabling the Caches

    M.Eladouly
    M.Eladouly

    Hello,

    I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9).

    In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches, MMU and Program Prediction.

    What I need is to know…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to know if a RAM is compatible with an architecture or a processor?

    wchgoldbach
    wchgoldbach

    I don't have much experience in building an embedded system from 0. I want to ask a general question as showed in the title through an example.

     

    I choose Cortex-A9 (ARMv7-Profile A architecture) as CPU.  Then I want to use DDR3 RAM of Alliance memory…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to use neon libraries ?

    TheLazy
    TheLazy

    Hi,

    I am working on an optimization project on Udoo board. I have to optimize a video shot detection code to work in real time. My Udoo board has i.Mx6 Cortex-A9 processor. I started working on optimization and have optimized the code upto 135ms per frame…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Using PMU on cortex-a9 CPU

    wagner
    wagner

    Folks,

    I am trying to run linux 'perf' on a new board with 2 ARM cortex-a9 CPUs. After compiling the kernel to include perf tool, i run 'perf stat true' and it returns valid stats. But when I run 'perf record' to profile my program, it doesn't record…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Can't find many microprocessor manufacturers with Cortex-A7 architecture?

    Omid
    Omid

    My understanding is that ARM Cortex-A7 architecture was released after Cortex-A9 and improves features of previous versions. However, I have only found one manufacturer, NXP, that uses Cortex-A7 architecture in their processors. I am referring to manufacturers…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Pipeline and Reorder Buffer on Cortex A9

    andTo
    andTo

    Hi everyone,


    For research reasons, I'm looking for information about the Cortex A9 out-of-order pipeline and the renaming of registries and any other data structures, if any, such as the reorder buffer (ROB).

    The Technical Reference Manual only names…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • The process of initializing ddr and other things on Cortex-A9

    Dean_Runov
    Dean_Runov

    Good afternoon!

    I work with Cortex-A9 and try to load the primary bootloader through the JTAG ARM-USB-TINY-H. For download, I need to know the sequence of entries in the registers to initialize the ddr, pll,uart. Where can I find the source to see all this…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Arm Neon not vectorising nested loop

    Syed Zabi
    Syed Zabi

    Hi,

    I am using A9 Processor on Zynq Board running a test project with neon and simd options enabled . In my code i have nested loops which is not vectorised and below is the build log 

     not vectorized: multiple nested loops. 

    Can anyone help me on thi…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • L2 Cache(Pl310) initialisation sequence

    Shravan Alugala
    Shravan Alugala

    Hi ,

    I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core.

    Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn't see any Drhit,Dwhit event count register gets updated…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • r0 corruption while making subroutine call on Cortex A-9

    teamrtos
    teamrtos

    Hi,

    I am running a bareboard code on i.MX6Quad board (It has Cortex A9 processor). The code is written in C and invokes function A in a while loop. Function A invokes Function B with 3 arguments.

    After some cycles (around 100-200 cycles) of while loop…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Issues in Cortex A9 bareboard code if L2 cache controller registers are not mapped

    teamrtos
    teamrtos

    Hi

    I have written a bareboard code for i.MX6 (Cortex A9 Quad core). I am activating and using only one core.  Once I enable the MMU, code throws random exceptions. Both L1 and L2 caches are disabled. The interesting part is that if I just map the memory…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Number of performance monitoring units in ARM Cortex A-53 and A-9

    user
    user

    Home many performance monitoring units (PMU) are in ARM Cortex A-53 and A-9? Is there a single PMU for each core or single PMU for the whole processor?

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A9 SCU Control Register Enable bit 0 or 1 for enable changed in Manual from g to h?

    NOTAN
    NOTAN

    The Cortex-A9 MPCore Technical Reference Manual Revision: r4p1

    describes the Bit 0 of scu-control-register  as   0 SCU enable 1 SCU disable. (this is Version i of the manual)

    In Version g of the manual ist the other way round (1 SCU enable 0 SCU disable)…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How do I probe in for Power measurement in A9 using PAPI tool

    Bharadwaj Gorthy
    Bharadwaj Gorthy

    Hi,

    I am new to the forum and also to the community. I am trying my best to reach out for help yet meeting the standards of the community. I have been working on ARM Cortex A9 MPcore processors that are on-board the Zedboard ( which is a Zynq Evaluation…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
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