Hello ;
I am working on Arm Cortex-A53 and here is the problem;
when ı am trying to allocate
A= new comp[N]; >>
typedef std::complex< double > comp;>>
#include <complex>
struct complex<double>
{
typedef double value_typ…
Hello ;
I am working on Arm Cortex-A53 and here is the problem;
when ı am trying to allocate
A= new comp[N]; >>
typedef std::complex< double > comp;>>
#include <complex>
struct complex<double>
{
typedef double value_typ…
Hello,
I'm trying to get MMU working on Cortex-A53. But still fails since at least 3 days. :(
I created following tables:
Level 1
0 0000000010006003 1 0000000010007003 2 0000000010008003 …
Hi,
I trying to switch from EL2 to EL1 on Cortex-A53. But it doesn't work.
Here is my current startup code:
#include <asm.h> IMPORT_ASM(_cpu_el3_vec_tbl_set) IMPORT_ASM(_cpu_el2_vec_tbl_set) IMPORT_ASM(_cpu_el1_vec_tbl_set) IMPORT_C(init…
Hello Sir,
We are using the liaro's aarch64-linux-gnu-gcc compiler, (version = gcc-linaro-6.3.1-2017.02-x86_64_aarch64-linux-gnu) for cross compiling for armv8, Cortex A53. We use many libraries, one of them is openssl-1.0.1p which supports max till armv7…
I'm debugging the ARM Cortex A53 on the QEMU emulator using gdb debugger, any idea on how to get what exception level I'm running on (EL3/2/1/0) ?
Hello,
I am trying to enable stage 2 translation on Raspberry Pi 3B+. I create a translation table, store its base address in VTTBR, configure VTCR and HCR to enable stage 2 translation.
These steps should be finished in EL2, but it hangs, without any…
Hi,
imx-atf allows alternative boot flow by preloading a BL33 (custom) image into memory.
Are there any instructions on how to use BL2 to boot an EL3 payload for pre-production test work ? How to use EL3_PAYLOAD_BASE common build parameter ?
Also, there…
I have a development board of NXP that has 4 x A53 cores and 1 x M7 core. I want to run 2 different OSes on the boards that are independent of each other. And my goal is to boot the processors separately without having dependence of the other core for…
Hi,
I can build bl31.bin for my i.MX8QM EVK (Arm Trusted Firmware open source reference) which can act as an Armv8-A bootloader.
I am NOT intending to include any u-boot binary in my test image. Is this possible ?
Can anyone suggest how to build a Cortex…
I'm using a IMX8QM system which features a dual-core A72 cluster plus a quad-core A53 cluster. Running on EL2 from one of the A53 cores I want to unmap a single page for all cores, so after I remove the entry for the page table I use the tlb invalidation…
Hi Arm community.
I'd like to get a development board with Cortex-A53 processor to develop, test and verify some audio algorithms. I'm working on Windows+Cygwin+Eclipse, so the board should be easily used with these tools. It should also be well documented…
When debugging my bare metal app I'm getting an exception I don't understand.
The processor is the Cortex-A53
The Exception occurs on "str q0, [sp, #96]"
When reading ESR_EL1 i get 0x1FE00000
so, the exception class is 0b111111
which…
Hi All.
Does ARMv8-A has something similar to VC_CORERESET bit in Debug Exception and Monitor Control Register of ARMv8-M ; which enables halt on reset vector on warm reset?
Or is there any other method to halt the ARMv8-A core in reset vector?
hi.
I have a question about floating point performance relative with fpsr register.
When i initialize hardware, there is floating point exception(inexactly floating-point exception).
I did not set fpcr.IXE=0, so fpsr.IXC is set. not occur exception.
…Hi,
I'm searching for the documentation for the exception classes in ESR_ELx. But currently couldn't found any information.
Want to port my bare-metal applications to AArch64. I own a PINE64 Rock64 (quad core Cortex-A53) board, which I want
…Hi
I study coresight test with cortex A53 CPU.
I get FIQ interrupt when I running helloworld test in ini_libc function. But I don't known why.
I use gcc-linaro 4.9 toolchain : aarch64-none-elf-gcc with glibc 2.14
Set CPU config pin aa64naa32 to 1…
There is a reference to erratum 820719 in the NXP S32V Errata list but I can't seem to find any reference to this erratum anywhere in ARM documentation. Is this erratum still valid?
Excerpt from S32V Errata document (refer: https://www.nxp.com/docs…
Hi,
I am using IDE Xilinx SDK 2019.1 for my application and running it on ARM cortex a53 processor with Neon and floating point engine support available. I am working on a bare metal application.
The problem I am facing is that, I am unable to understand…
I am using ARMv8 GCC compiler(aarch64-none-elf-gcc) for my bare metal application on ARM cortex a53. I am using neon intrinsics with plain C in my code so I would like to ensure to use all optimization option available for this compiler.
I tried -mfpu…
I am using ARMv8 GCC compiler and I would like to optimize Neon Intrinsics code for better execution time performance. I have already tried loop unrolling and I am using look up table for the computation of log10. Any ideas?
Here is the code:
static inline…
Hello,
we have a board using Armada 3720 SOC, which contains two Cortex-A53s and one Cortex-M3 used as secure-coprocessor. The interrupt controller is GIC-500.
The M3 has access to all registers that A53 can see. The first A53 has RVBAR at 0xffff0000 where…
Dear Experts
I am working on a target that contains quad A53 cores operating at 1GHz. The operating system idle loop contains WFI inline assembly instruction. I know that the Core Clock halts during the WFI instruction which can be seen on the PM_CCNTR…
In the ARM Architecture Reference Manual issue D.a (ARM DDI 0487D.a) section K11.3.1 "Acquiring a lock" has the following example code:
AArch32
Px
PLDW[R1] ; preload into cache in unique state
Loop
LDAEX R5, [R1] ; read…
Dear All,
I am using a raspberry pi B+ that uses a Broadcom BCM2837 SoC with an ARMV8 processor. I want to get the cpu temperature in a Linux kernel file. Like in x86, I can use rdmsr_on_cpu function to load the temperature from MSR_IA32_THERM_STATUS register…