• CP15SDISABLE

    AALLeeXX
    AALLeeXX

    Hello,

    it maybe not the right place to ask, but friends on PI forums seem not aware either so, i ask here in case;)

    The question is simply, where is this input mapped on the raspberry PI2 ? Is it a conventional input ? Is it really mapped or implemented…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • is there any simulator for ARM CORTEX A series

    dhrumil Shah
    dhrumil Shah

    I was working on smart wearable using ARM Cortex A series so there is any other simulator for ARM CORTEX A

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to execute 32-bit ARM assembly in a 64-bit environment

    sandrosart
    sandrosart

    Hi everyone,

    I have a 32-bit arm assembly program and I'd like to run it in a 64-bit os (in particular, in a raspberry pi 3 board). Which libraries do I need in order to do that?

    Thanks in advance.

    Sandro

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Memory read error at 0xF8000008: Cannot read write-only register.

    doner_t
    doner_t

    Hello, 

    I am not sure, here is correct place to ask this question. But I want to try ; 

    I have received an error :  Memory read error at 0xF8000008: Cannot read write-only register, When I try to debug a basic memory test code, in CortexA9.  I can not even…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?

    thomas_cp
    thomas_cp

    Hi, 

    I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

    The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

    There is no L3 cache. So the memory…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A53 : Cache policy setting

    PrabhuKrishnan
    PrabhuKrishnan

    Hi,

    Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor? 

    I'm enabling the caching using the SCTRL register and in the MMU configuration table, I'm setting the memory…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • [A53] Hex file is Huge when generated fromo ELF

    AshishK
    AshishK

    Hi , 

    If I generate the elf file from the Default bootcode and pagetables , I get a very small size but 

    after mapping the Stack pointer to SRAM , I am getting a huge HEX file. 

    Here is the  loader file  code 

    ============================================…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Trying to find basic performance measurements of ARM cores

    eskimoalva
    eskimoalva

    Howdy, I was trying to find some basic performance benchmarks for a couple of different ARM cores: The Arm 926EJ-S, Cortex A9, and the Cortex M7.

    I am looking for primarily DMIPS (per MHz or a form that requires me scaling to my specific chip is fine…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Launching bare-metal firmware at EL2 (Hyp) on QEMU with ARM Trusted Firmware?

    gcicero
    gcicero

    Hi experts,

    I am recently developing some bare-metal code for a Cortex-A57 Aarch64 on QEMU (Virt platform) for playing with the Virtualization Extension. I first used one core and I developed a bootloader from scratch that switches the execution from…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • [Cortex-A53] STP instruction stores out of the specified memory

    Emmy0
    Emmy0

    Hi Experts,

         I have a question about "STP" instruction in Cortex-A53.

         STP W6, W6, [SP, #20]  --> after it executes, the memory of [sp, #16] and [sp, #28] are corrupted.

         I don't know why cause it. 

        Can you help to explain the reason…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • SMC not going into EL3

    yaron alterman
    yaron alterman

    Hello experts,

    In my project I need to write some bare metal code in order to boot my software (A VxWorks image), and would like to make the absolute minimum configurations before loading the VxWorks image, which then does the major part of the configurations…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM cortext A53 Physical Address Flush

    m0sf3tz
    m0sf3tz

    Since ARM caches are physically indexed is there any way to flush based on the PA? I know I can get the set, but what about the way? If I am flushing from L1 would I have to flush all ways in L1 and then L2 assuming there is no L3 to get to system memory…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex A9 - Enabling/Disabling the Caches

    M.Eladouly
    M.Eladouly

    Hello,

    I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9).

    In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches, MMU and Program Prediction.

    What I need is to know…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Interrupt collector

    RCReddy
    RCReddy

    Hi All,

    I am using Arm Cortex-A53 based board.I modified a driver module and the interrupt processing.

    I have a fundamental question:

    Since Arm Cortex-A53 can handle 16 primary interrupts, what happens if all the interrupts arrive at same time. Though…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to know if a RAM is compatible with an architecture or a processor?

    wchgoldbach
    wchgoldbach

    I don't have much experience in building an embedded system from 0. I want to ask a general question as showed in the title through an example.

     

    I choose Cortex-A9 (ARMv7-Profile A architecture) as CPU.  Then I want to use DDR3 RAM of Alliance memory…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A53 backward compatible with AXI-4 interconnect

    Ed Leung
    Ed Leung

    Hi,

    The Cortex-A53 core supports either ACE or CHI as its master interface.  Assuming I don't need any of the coherent features introduced in the ACE specification, is there any functional problem if Cortex-A53 ACE interface is connected to an AXI-4 interconnect…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • System level Implementation of Generic Timer in Cortex A53

    Vasu
    Vasu

    Hi,

    Im new to ARM. Im learning generic timers in cortex a-53. I wanted to know whats the meaning of "system level implementation" of Generic Timer and "PE implementations" of the Generic Timer.  How is it different from Generic timer…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How memory mapping is done

    foxem
    foxem

    Hello, sorry if i posted in the wrong forum.

    I would like to know how memory mapping is done, that is to say which software/hardware component allow me to write for exemple into the address 0 of the flash memory in using the address 0x20000000 in my code…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Load / Store timings with different cache settings

    superdesk
    superdesk

    Hello,

    I am timing load and store instructions for baremetal program by stepping though execution using OpenOCD and using the PMU cycle counter with single cycle granularity. I am running the program on a single core of a Cortex-A9 on a Xilinix Zynq-7000…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Generic Timer in Cortex A-53

    Vasu
    Vasu
    1. What is the input & output of system counter? What is it's purpose? How to start/stop it?
    2. What is the input & output of Physical counter? What is it's purpose? How to start/stop it?
    3. What are the differences between Physical Counter &…
    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8: strongly ordered memory and exclusive access

    Vincent Siles
    Vincent Siles

    We are developing a bare metal secure OS on a NXP LS1043a board, with a Cortex A53 v8 core.

    While debugging some issue with DMA, I decided to switch all kernel mapping from Normal cacheable to Strongly ordered (Device-nGnRnE memory type) and then witness…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • could anybody help me to write a bare metal startup code for LS1043A (ARM V8,A53)in 32bit(AARCH32)mode

    RanadeepReddy
    RanadeepReddy

    excuse me for my English!!!

    i want to write bare-metal startup code in 32-bit mode for LS1043A-Rdb.it is having V8 A53 core.

    i have bare-metal 32bit(AARCH32) code for xilinx processor(which is of V8,A53core).How much of that code is useful to write code…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • help me to understand this assembly program for configuring MMU for ArmV8,A53.

    RanadeepReddy
    RanadeepReddy

    ******************************************************************************/
    /*****************************************************************************/
    /**
    * @file translation_table.s
    *
    * @addtogroup a53_32_boot_code
    * @{
    * <h2> translation_table…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • about cortex-A72

    Kallooran
    Kallooran

    hello guys, can you tell me the number of execution units in Cortex-A72 and the number of clock cycles it takes per instruction?

    Thanks in advance

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Using PMU on cortex-a9 CPU

    wagner
    wagner

    Folks,

    I am trying to run linux 'perf' on a new board with 2 ARM cortex-a9 CPUs. After compiling the kernel to include perf tool, i run 'perf stat true' and it returns valid stats. But when I run 'perf record' to profile my program, it doesn't record…

    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
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