Say, like Time Stamp Counter of x86, or Time Base of PowerPC, which can used to
do some performance profiling.
Say, like Time Stamp Counter of x86, or Time Base of PowerPC, which can used to
do some performance profiling.
Hi Experts,
Is there any document on general software guidelines in reducing the cache miss rate in the system for ARMV7 architectures ?
If it is more specific to A/R/M then its great..
Hello,
Is there any data regarding the minimum and maximum frequency a processor can operate in ARM V-7 ?
Hi Experts,
Which factor in processor decides whether it can be used in multi-core or not ?
Like as per my understanding A8 is used in single core whereas A9 is used in multi core. So which distinctive feature in A9 favors the multi core application ?
hi, experts:
I found ACTLR register definition is different between Cortex-A7 and Cortex-A9.
I have some questions about out cache concept in Cortex-A7.
1. Some program disable outer cache by setting ACTLR[1] = 0.
So, is it only available with Cortex-A9…
Hello all,
I have a client who has the following requirement. He uses an Cortex A9 (dual core) based SoC chip .
The system has two Flash ROMs - Flash ROM 0 and Flash ROM 1. Each of these flash roms has a boot loader and user program.
On Reset, the CPU 0…
Hi,
I just got a raspberry pi 2 and I'd like to play with Trustzone.
People on the Raspberry forum http://www.raspberrypi.org/forums/viewtopic.php?p=697474#p697474 explained me how to
get my hand on the boot of the 4 core A7 CPU, and I managed to boot…
greetings,
as i know the boot loader is the start-up for most of controllers today. till now i just used the boot loader written by someone but i don't have any idea about it how to write it what are the things we have to include and what…
hi,
I'm studying Cortex-A53 cache process. I run the following cache invalid program, but the result is cache not invalid.
Could you give me any suggestion about cache invalid? Thanks!
The program…
In RTL code of A9mp platform provided by ARM, I see that almost all registers are renamed and are out of order(There are registers named R0-R55). This make it quite difficult for me to debug some problems.
So how can I match them with R0-R14, especially…
Hi Experts,
How to derive the cache memory requirement for the working of the software ?
I could understand that each of the A/M/R processors have its own applications and build with its own Cache size MPU/MMU configurations but how this is derived with…
Hi,
I am new to the ARM community. I am currently studying the HSA (Heterogeneous System Architecture). ARM is member of this foundation.
I wonder which processor from ARM is HSA enabled? And on which devkit (raspberry, ODROID, or other) So I can use it…
Hello All,
I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU.
Issue 1:
But what I could notice is code region in external ram is executing faster than internal ram.
If I disable…
Hi folks,
The technical reference states that only a subset of possible AXI transactions are actually generated.
This is described in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Babiaggf.html
What happens for this table if the master…
Dear ARM Group,
Can we run the A53 cores at different clock speeds?
if YES, How does it effect the complete A53 (L2 cache etc) and system?
if NO, What are the constraints ?
could you please give a detailed description on this?
Thanks,
Ravinder…
as we know supervisor mode is priviliged and user is not. at reset time in debugging mode, i read the cpsr it is 0x1d3 means in supervisor mode, so i can change CPSR so i changed it to 0x1d0 which is user mode, since user mode is unpriviliged so i must…
Hello,
I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I the system there will be a cortex A7 master(64bytes cache line). My question is: in case of such transaction (WriteLineUnique with 128bytes…
Hi,actually i need to run big endian code but i don't know how to set endian option in cp15 registers could any suggest me how to set EE bit set
Hello,
i want to use the arm cortex a9 to share memory between both cores. are there any examples online?
Thanks,
Mike
Hi Experts,
Whether the ARM provides the power management controller inbuilt in the cortex A5x processors or it provides signal pins suitable for easy integration with the power management controllers ?
Hi Experts,
What is the use case of split/lock configuration in the Application processors ?
I'm testing GIC and ARM A53 connectivity. I can see that GIC is forwarding the IRQ request and ARM core has received it(shows in ISR reg). However, my IRQ handler is not getting called. Here is how I'm registering it..
void main () {
...
__enable_irq…
When using gcc to compile c code for ARM platform, we set object platform by using:
-mcpu = xxxxxx
To what extent will that affect results of compiling ?
For example:
-mcpu = cortex-a8
and
-mcpu = cortex…
Hi Experts,
Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ?
I found some features like CCI module available to provide this feature in multi-core environment. Other than that, is it possible…
Hello all,
I have a A53 based platform. There are multiple IRQ sources, some of which fire at the same time. To avoid recursive IRQ handler calls, I have disabled IRQs' on entry in IRQ handler and enabled them befor exit. However, at one point, there is…