• which ARM version that i should use for PLC

    houssam
    houssam

    hello !

    i am houssam an electrical engineering student, i am new to this forum and new for ARM processore i want to make my own PLC (programable logic controler), and i need a processore for to build this PLC, i find a lot of type of ARM processore (cortex…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Barriers in in-order cores like cortex-A53, A7

    oootha
    oootha

    Hi experts!

    As you know, power efficient arm like cortexA7, A53 has in-order pipleline.
    However as far as I understanding, Barriers like dmb, dsb, isb are related with out-of-order memory access.
    But barriers are even used in in-order cpus.
    What is for?
    Can…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to configure L2 cache in Cortex-A7

    Cherma Rajan
    Cherma Rajan

    Hi all,

    I am working on OrangePi board. The board configuration is,

    • Quad-Core ARM Cortex-A7, 1.6 GHz
    • 32 KB L1 I-Cache and 32 KB L1 D-Cache per core
    • 512 KB L2-Cache

    I have few queries related to Cache memory,

    1. How to disable L2 cache of Cortex-A7 in…
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • CORTEX-A processor interrupt handling

    Girish Raghavendran
    Girish Raghavendran

    Since I am currently reading lot of ARM documents to understand the architecture as a whole, I request you to mention as to what happens in case of CORTEX-A processor in the nested interrupt handler implementation since we have a SPSR in CORTEX-A processors…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • TZASC (TZC380) enabling sequence

    Vincent Siles
    Vincent Siles

    Hi everyone, I am trying to correctly setup the TZASC of my IMX6q and IMX6ul boards, without blowing the fuse (I only have one board, I'd like to have it right by software before).

    From what I gathered from the documentation of the TZASC and from the…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cannot access EL1 resources from EL3 or secure world on armv8.

    Tgn Yang
    Tgn Yang

    The working secerio is that I'm testing OP-TEE on a Hikey board(Cortex-A53, armv8), and they use arm-trusted-firmware(see https://github.com/linaro-swg/arm-trusted-firmware) to be the monitor running in EL3.

    I'm trying to access some resources in EL1…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to configure Cortex-A57 PMU

    Michael
    Michael

    I asked this question in a different community space but it seemed like this is a more appropriate home.

    I'm trying to configure the performance counters for the Cortex-A57 and I'm very confused. The technical reference manual alludes to accesses being…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What is differene between cortex A, Cortex M and Cortex R series of ARM?

    tanveermalik
    tanveermalik

    Hi everyone,

    I want to start learning microcontrollers and embedded linux? I want to ask what is differene between A, R and M series of ARM microcontroller? Kindly also suggest me a good book to start learning ARM microcontroller? Which board should I…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Need to invalidate L1 cache after DMA on Cortex A9

    Rohan
    Rohan

    Hi,

    I'm using a Renesas RZ/A1L, Cortex A9 microcontroller. After a DMA operation which transfers some data from a SPI module into RAM, I can't read the data correctly unless I've disabled L1 cache. (The base code which Renesas supplies sets the caches…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What does PMCEID0_EL0 determine for the the PMU? Performance monitor config

    Michael
    Michael

    The TRM for the a-57 states that PMCEID0_EL0: Defines which common architectural and common micro-architectural feature events are implemented. PMCEID1_EL0 is a continuation of this list. If a bit position is a "1" that means the even is implemented…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Embedded assembly function problem

    Andrea
    Andrea

    Hello all,

    I wrote end embedded assembly function for an ARM Cortex A9 (the specific device is Zynq, from Xilinx) as follow

    float my_fun(float x)

    {

                    asm volatile ("vdup.f32 d0, r0                     \n\t");…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • SGIs in AMP Configuration with Non-SMP Linux /RTOS

    Shafique
    Shafique

    I am trying to run two Cortex-A7s in AMP configuration with Linux running on one core (SMP disabled) and baremetal/RTOS running on other core. I am having difficulty in setting up SGIs (IPIs) between the two cores. I am at a point where both of the cores…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Please, request for Cortex-A53 processor..How can I buy it?

    강소연
    강소연

    Hello?

    This is SoYeon Kang.

    I'm Korean.

    I want to purchase

    Cortex-A53.

    How can I buy it???

    Then, I want to ask

    for the cost of Cortex-A53.

    What's the one product cost?

    Then, how much several product costs?

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to use generic timer/counter

    Michael
    Michael

    The technical reference manual states that the Cortex-A57 generic timer events are not affected by CPU clock frequency change. My challenge is that I can't use any built in linux libraries to create a delay because whenever I try it clears performance…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex A9 second execution unit

    Kushal
    Kushal

    Dear All,

    I am trying to understand the full working of execution stage in ARM cortex A9 and the types of instructions that are executed in second execution unit(ALU).

    Till now i was able to find quite limited references that were not much helpful.

    If any…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Trustzone and Hardware virtualization support

    Justin
    Justin

    Hello,

    I am looking for a development board that has an open Trustzone and hardware virtualization support. Do the Juno boards support this?

    Looking around the ARM A72/57/53 chips all support Arm Trustzone and have hardware virtualization support, however…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • voltage levels for dvfs

    Hergys
    Hergys

    Hello,

    i was wondering if the voltage levels for dvfs states are fixed at the design time. For example for Cortex A7 or A15. Is this information available?

    Thank you.

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Data Abort Exception in A53

    Geeta Phuloria
    Geeta Phuloria

    Hello,

    I am working on Cortex-A53  and using Cortex-A53 DSM Model in my design. We are getting Data Abort exception on a read to ROM address and ESR_EL3 register showing its a DECERR External error. MMU and Cache both are not enabled at this point where…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is it possible to read the raw L1/L2 cache data and tag bits on the Cortex-A9?

    Alex W
    Alex W

    I've been digging through the Technical Reference Manual (TRM) for the Cortex-A9 and so far it seems that it's possible to gather data about events such as hit and miss rates, but there doesn't seem to be anything on reading the raw data and tag bits…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Differences between Privilege Modes and Non-Privilege Mode ?

    Rui
    Rui

    Hi everyone ,

    I'm currently using a Cortex-A9 processor (NXP Freescale i.MX6S).

    My project is to develop a simple OS, but I met a problem:   

    When I am trying to control some peripherals (such as UART and GPIO) directly under ARM USER MODE, the program…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to modify the value of AWCACHE [3:0] and ARCACHE[3:0] in AXI?

    zynq
    zynq

    hey,

    How to modify the value of AWCACHE [3:0] and ARCACHE[3:0] in AXI?

    in baremental driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x00,

    but in linux driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x01,

    can anybody tell me…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A53 direct access to cache: How are instructions encoded in the L1 I-cache?

    Alex W
    Alex W

    The TRM for the Cortex-A53 has a section on direct access to various internal memories, including the L1 I-cache and D-caches. I'm successfully able to dump both tag and data for the I-cache and D-cache, but I'm having trouble making sense of the I-cache…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Secure world entry request by normal world application

    Shane Yu
    Shane Yu

    For a TrustZone enabled processor, what if a normal world application (e.g. 3rd party application) directly uses SMC instruction to request a secure world entry? In a typical case, it it a responsibility of monitor SW or Secure OS kernel to authenticate…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Getting started on Cortex A5 interrupts

    Markus
    Markus

    I'm new to Cortex A5 and I'm trying to figure out how the interrupts work.

    From my understanding, the Cortex A5 starts in secure mode and I don't change it. Now I set up the "secure interrupt controller" (of course only accessible in secure mode…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Where is hardware interrupt latency documented for the ARMv8 Cortex-A53?

    Tracy Smith
    Tracy Smith

    Need specific references to the hardware interrupt latency for the ARMv8 Cortex-A53.  interrupt latency from when an interrupt is triggered to when the ISR is initially invoked, but not including operating system, kernel, or application latency.

    …
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
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