• Porting C code (using intrinsics) from Cortex-M to Cortex-A?

    DanijelDomazet
    DanijelDomazet

    Hi, I am looking at ARM CMSIS code for biquad float32 implementation. This is written for Cortex-M as documentation states. How much effort would be needed to port this code to Cortex-A53? The code should be fast, optimized using intrinsics, not assembly…

    • 7 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • What can cause getting Cortex-A55 DSU P-Channel PACCEPT/PDENY signals fail?

    Emmy0
    Emmy0

    Hi experts,

    I do an experiment about cpu power with a board which has 4 cores of Cortex-A55.

    I try to power on/power off core1~3 parallelly.

    Sometimes Both PACCEPT and PDENY are zero after changes the power state.

    If I only power on/power off one core,…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Secure SPI : STM32MP157-DK1 board

    Simon
    Simon

    Hey everyone,

    I am working on STM32MP157-DK1 with trustzone cortex-A.
    I want to use the SPI in secure side, but it's possible only with SPI 6 that is not mapped to the outside.


    It's possible to activate SPI (1 ... 5) peripherals in secure side ? if…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Running two bare-metal programs on two separate cores in Cortex-A9

    Adeeljs
    Adeeljs

    Hello,

    I have run two different bare-metal programs on two corresponding ARM cores in Cyclone V (Cortex-A9) in DS5 using JTAG line. The SDRAM is shared between the two cores as is evident from the cache settings which is set to "shared" by default. Core…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • NEON in Cortex-A8

    Mallikarjun Shivappa Bidari
    Mallikarjun Shivappa Bidari
    Note: This was originally posted on 20th February 2009 at http://forums.arm.com

    Hi,

    I am working on Cortex-A8 processor, this has NEON coprocessor.

    Its possible to execute the Multimedia (like Audio, Vidoe, Graphics.....) components in NEON.

    Is it possible…
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A8 Problem with RVDS or ARM GCC?

    Ranjith Kumar
    Ranjith Kumar
    Note: This was originally posted on 4th March 2009 at http://forums.arm.com

    Hi All,

              My application is not running in ARM Cortex A8. But same application is working in ARM9e. I have compiled using --cpu=cortex-a8 or --cpu = 7-a. Is their any specific…
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Memory partitioning on Cortex-A7

    Man-Ki Yoon
    Man-Ki Yoon

    Hello,

    I am using a quad-core Cortex-A7 (on Raspberry PI 2). I run a Linux on Core 0,1,2 and a baremetal application on Core 3. My goal is to protect the baremetal application from the rest (i.e., the linux side). Initially I thought that I can do this…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • how to know the specific cycles of every arm instruction (armV7,cortex-a8) while executing in asm file?

    Meng
    Meng

    how to know the specific cycles of every arm instruction (armV7,cortex-a8) while executing in asm form?

    if there are some documents which describes it in detail?

    In Chinese:

    我目前用cortex-A8(armV7)来开发项目,由于一些算法需要在ARM端跑,算法需要优化,需要写arm汇编指令,

    想知道,armv7每个指令执行消耗的周期…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Multicore SMP using Linux kernel

    manish
    manish

    Hi,

    I am just trying to learn the linux kernel booting process for arm32 Cortex A9 multi core SOC. I had understood the concept of booting in linux, but I am confused about the section where secondary cores enabling from primary core. Can somebody briefly…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Question about program flow prediction

    alireza11048
    alireza11048

    I am examining ARM Cortex-A8 program flow prediction abilities, in document of Cortex-A8 arm specified that it would predict LDM instruction with PC in register list. now i have a question, if we have some condition in the instruction, such as "LDMGE…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Arm Cortex-A8 program flow prediction

    alireza11048
    alireza11048

    I am examining ARM-Cortex A8 flow prediction abilities, in order to done this i implemented below code:

    char SecretDispatcher[256 * 512];
    int counter = 0;
    
    //evicting SecretDispatcher from cache
    ...
    
    while(counter < (512 * 9 + 1))
    {
        //evict…

    • Answered
    • over 1 year ago
    • Processors
    • Classic processors forum
  • Shifted binary generated by arm-none-eabi-objcopy

    en2senpai
    en2senpai

    Moved to:

    https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/43775/shifted-binary-produced-by-arm-none-eabi-objcopy

    • Answered
    • over 1 year ago
    • Processors
    • Classic processors forum
  • Why do we have to send HMASTLOCK signal to the slave?

    Hyunkyu
    Hyunkyu

    In AHB-Lite cases, every transfer starts with address phase with signals from master.

    And also in multi-master cases, arbiter decides with whether it can GRANT bus access to other masters or not.

    So, I think it's fine to only let masters or arbiters to…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex-A9 | Non-cacheable memory range

    S R Chidrupaya
    S R Chidrupaya
    Note: This was originally posted on 23rd May 2013 at http://forums.arm.com

    Hi all,


    I am designing an application on  xilinx zynq 702 board which comes with two(core) arm cortex a9 processors. I am using one of the arm cores two run a part of the application…
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • The exact definition of outer and inner in ARMv7

    Jaeyong Yoo
    Jaeyong Yoo

    Hello,

    I'm reading ARMv7 architecture reference manual and there are the following keywords:

    • outer cacheable
    • inner cacheable
    • outer sharable
    • inner sharable

    It looks like that outer/inner cacheable means that a region of memory can be cached in L1…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI SLAVE PERIPHERAL

    Antonio
    Antonio

    Hi everyone! Please help me.. i have  a project with a custom axi slave  design that  implements multiple memory ranges 256 words each . A master ( my processor in figure) can write burst data to the example slave and read the data back. The problem is…

    • Answered
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • unaligned data fetch in Cortexa9

    anoop
    anoop

    I have a question related to data fetch, when on gdb debugger I do an address read say as:

    X 0x81000000

    Then it will fetch 64 bits as you told in reference to Cortex A9

    If further I do

    X 0x81000004

    Will it fetch 64 bits  again from 0x81000000 or it will use…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • New to ARM and having trouble locating example folders - help please ;)

    Matthew Jones
    Matthew Jones

    Hello Everyone,

    I am new to ARM processors.  I am trying to get a good handle on the low levels aspects of the ARM processor like exception handling.  From searching the ARM website and looking at the data abort handler documentation I am pointed to this…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What is the difference between ARM cortex-A and cores in snapdragon from Qualcomm?

    Nitin Bhaskar
    Nitin Bhaskar

    Hi All,

    What is the difference between ARM cortex-A and cores in snapdragon from Qualcomm? I know that they say it is compatible with ARMv7/8 ISA.

    Regards

    Nitin

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv7-A: What is "Fault not on a stage 2 translation for a stage 1 translation table walk"?

    Takumi Shimada
    Takumi Shimada

    Hi all,

    I'm trying to boot Linux on my hypervisor like environment.

    In booting process, unexpected hyper trap was occurred and became hyp mode.

    In hyp mode, the Hyp Syndrome Register (HSR) value is 0x93830006.

    According to the manual, this meant "Fault…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Question -

    Michihiro Yamamoto
    Michihiro Yamamoto

    Hi,

    I have strange symptom with Cortex-A15 device.

    The below is traced data.

    Program AddressDisassembly

    0x40401AA0CMP             R12, R0

    0x40401AA4BHI             0x40401A80…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How many clock cycles do SVC/PUSH/POP/SRS/RFE insturctions take to execute on Cortex-A8 processor?

    Jooyoung Jung
    Jooyoung Jung

    I'm trying to count the cycle timing of my program in hand.

    I read the ARM Cortex-A8 R3P1 Technical Reference Manual: Chapter 16. Instruction Cycle Timing, but I couldn't find the cycle timings of SVC/PUSH/POP/SRS/RFE.

    I want to know how many clock…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What is real application of Exclusive access in AXI

    Koteswara Rao P
    Koteswara Rao P

    Hi,

      What is real time application of AXI exclusive access.

      Is it necessarily to do Exclusive read first then exclusive write.

      May i know the reason is it so?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to handle SCU at runtime on Cortex-A9

    John
    John

    Hi there,

    I'm working on altera cyclone V SoC equipped with a Dual Core Cortex-A9. It runs Linux socfpga 3.13. I'm trying to disable (and enable) the SCU at runtime, but I have a segmantation fault: unable to handle kernel paging requet at virtual address…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Aarch32 app performance on ARMv8a device

    Sreenath P V
    Sreenath P V

    Hi ,

    I am running aarch32 app in ARMv8a( cortex-a57 ) device.  The performance reports ( using gettimeofday() utility ), showing  large spikes on random calls. But the same app on ARMv7a( cortex-a15 ) device is quite stable.

    Will the aarch32 library…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • View related content from anywhere
  • More
  • Cancel
>