I am cyclically filling the mmap-ed DMA buffer with my data by copying it from "normal" memory in 290 bytes chunks.
At the first cycle memcpy always passes OK. At the second cycle it hangs in __memcpy_neon routine (at least this is what the…
I am cyclically filling the mmap-ed DMA buffer with my data by copying it from "normal" memory in 290 bytes chunks.
At the first cycle memcpy always passes OK. At the second cycle it hangs in __memcpy_neon routine (at least this is what the…
hi, experts:
In Cortex-A57 TRM chapter 4.3.66 :
It defines CPUACTLR_EL1 register, but this register name is not CPUACTLR_EL1.
Its name is S3_1_C15_C2_0.
Why?
best wishes,
hi
Hi,
I have enabled the userspace pmu access by building a kernel module for both core on Cortex-a9. Then I follow the standard procedure of pmu counting:
1. Disable performance counters
2. Set cycle counter tick rate
3. Reset performance counters
4. Enable…
Can someone explain more about this issue, and please provide the fix for this issue.
hi, experts:
In ARMv8 Arch reference manual, it said:
ARMv8 supports cache lockdown feature, but it is implementation defined.
So, my question is:
Has the integrated L2 Cache controller some registers related lockdown feature settings?
I didn't find them in…
Hi,
I'm trying to implement a spin-lock to synchronize the execution of all cores Cortex-A53 on my Xilinx-ZCU102 board, but I have some issues maybe due to a wrong configuration of the VMSA and cache coherence.
I'm writing bare-metal code, without…
Hi,
I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE architecture. I find some articles that telling L1 and…
Hello,
I would like to know how to read the translation table info for A9 from embedded Linux.
In freeRTOS I have translation_table.S but I do not find anything similar for ARM architecure in linux kernel.
Should I just dump TTBR0/TTBR1 registers…
Brief explanation of each stage of ARM pipe-lining.
How many Neon pipeline stages are their?
What is dual issue in ARM pipe-lining?
I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib).
On the shared SDRAM, I am planning to have dedicated memory regions for each core, and a shared…
Hello there,
I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core.
I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and cache
Steps :
1.Disable cache, branch predictors
2. Invalidate…
when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thank's a lot!
Hi Expert,
I am working on a simple kernel and test it on Qemu which supports RasPi3. During the boot level. Ras Pi goes to EL3 level, and I set spsr_el3 to 1 and elr_el3 to kernel_main and then use eret to enter EL1 mode. My problem is I create a kernel…
Good morning, I'm studying ARM assembly, Cortex A series. Reading the ARM documentation I found out this paper (Cortex A8, fast memcpy examples). My attention went to the PDL instruction, preloading into cache. I have read about it on the ARM manuals…
I am looking to emulate an Apple II and would like to specify some address ranges as being memory mapped so that any access would result in perhaps an interrupt that I am then able to handle and in which I can determine the memory address being accessed…
I am implementing a small OS as a university project in a A9 chip (a Xilinx Zynq). I am using trustzone to implement some features and I want to pass through SVC calls from user mode directly to monitor, so I issue an SMC in my SVC handler. Here it is…
Hello community and experts,
I am doing an experiment on Cortex-A53 which executes some exclusive access instructions such as 'ldaxr'.
When I config memory to Normal type+cacheable, 'ldaxr' can execute well. But if I config memory to Normal…
Hi Experts,
I'm researching Cortex-A53 cache.
Can Cortex-a53 l2cache be enable/disable independently?
Is it possible to only enable l1 cache and disable l2cache?
Does cortex-a53 support l2cache lock function?
Thanks for your attention!
Best…
I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A kind of write-through / "no-allocate" policy?…
I'm looking to emulate a 6502 on the ARM but I would like to make it cycle accurate so I need some way to interface to an external clock. I can't rely on an internal clock as there are external components that will rely on the external clock as well and…
Hi all,
A Question about the A8 processor.
If I enable the L1 and L2 caches, I see a performance boost even if the MMU is disabled. I was under the impression that the MMU is required to be enabled to use the Cache. I also do not see any errors or mismatches…
Hello,
Can I assume that with cortex A8 cache invalidate/flush is used only with L1 ?
I have some 2 implementation of this routines, one is called L1 and the other L2C-310.
I am just not sure if using L1 will be good enough, or is it that cortex a8 internal…
Hi,
I am working on DM37xevm platform and already invalidate the L2 cache (256KB) using the code
asm volatile moveq r12, #0x1"); …
Hi guys,
I have a question regarding "Cache allocation technology" that is present in Broadwell processors of Intel. Does ARM (aarch32/aarch64) support similar way of partitioning the LLC for a process to access?