• determine a page size on armv8

    MarekBykowski
    MarekBykowski

    Hi,

    I have a need at determining a page size, particularly for a Non-secure EL1, stage 1. I know of 

    __asm__ volatile ("at s1e1r, %0" : : "r" (buf));    
    __asm__ volatile ("mrs %0, PAR_EL1\n" : "=r" (par_el1));

    …
    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • What is the difference between ARM cortex-A and cores in snapdragon from Qualcomm?

    Nitin Bhaskar
    Nitin Bhaskar

    Hi All,

    What is the difference between ARM cortex-A and cores in snapdragon from Qualcomm? I know that they say it is compatible with ARMv7/8 ISA.

    Regards

    Nitin

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8-A:TrustZone and MMU

    42Bastian
    42Bastian

    I wonder how VA->PA translation is handled from non-secure world with Aarch64.

    I see the HYP mode uses IPA so that the second stage translation may restrict the VM to certain memory.

    But what about limiting access to secure memory? Is it only possible…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • I'm not seeing any flush-to-zero (FTZ) effects with NEON intrinsics on an ARM A9, any advice?

    David L
    David L

    Hi everyone,

    As the title states - I've had issues reproducing flush-to-zero (FTZ) using the NEON intrinsics provided in the 'arm_neon.h' header. For test purposes I'm using an iPhone 6 with an ARMv8-A dual-core ('Twister') CPU.…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to configure Cortex-A57 PMU

    Michael
    Michael

    I asked this question in a different community space but it seemed like this is a more appropriate home.

    I'm trying to configure the performance counters for the Cortex-A57 and I'm very confused. The technical reference manual alludes to accesses being…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to use generic timer/counter

    Michael
    Michael

    The technical reference manual states that the Cortex-A57 generic timer events are not affected by CPU clock frequency change. My challenge is that I can't use any built in linux libraries to create a delay because whenever I try it clears performance…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to do the ARM state change between 64-bit and 32-bit?

    Prasad
    Prasad

    Hi,

    The latest 64-bit architecture can on both AArch64 and AArch32 state.

    Can someone tell me how to utilize this feature so that I can seamlessly integrate algorithms (which are optimized with 32-bit and 64-bit instructions) with applications which are…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Differences between Privilege Modes and Non-Privilege Mode ?

    Rui
    Rui

    Hi everyone ,

    I'm currently using a Cortex-A9 processor (NXP Freescale i.MX6S).

    My project is to develop a simple OS, but I met a problem:   

    When I am trying to control some peripherals (such as UART and GPIO) directly under ARM USER MODE, the program…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • how to return from exception generated by SMC instruction

    rajtx
    rajtx

    Hi,

    I am experimenting execution level switching on A53. I go from EL3->El2, then call SMC instruction to return to EL3. As soon as SMC instruction is executed, the processor enters EL3 mode and an exception is generated.

    I have written an exception…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8-A Instruction for Getting CPU Number

    Shengye Wan
    Shengye Wan

    Hi,

    I'm using a Juno r1 board and I'm trying to get processor's related CPU ID without using any header file like function sched_getcpu from sched.h.

    The reason is I want to get the CPU number for TrustZone application and there is no way to…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why does FPU performance differ in AArch64 and AArch32 with Cortex-A53?

    Yasuhiko Koumoto
    Yasuhiko Koumoto

    Hello experts,


    I have come to having a question.
    VFP Benchmark is a benchmark application which was made by a certain Japanese in order to measure ARM VFP performance especially for ARMv7-A and ARMv8-A.
    The software can be downloaded from the following link…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • why there are 4 cores per cluster in ARMV8 architecture

    RadarSong
    RadarSong

    Hi experts,

    I want to knows why there are 4 core cores per cluster in ARM big.Littte architecture?

    Is it possiable if we make more cores per cluster? if not, what is the limitation?

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why the address width of MMU-500 is different with Cortex-A53/57?

    wangyong
    wangyong

    I find the description below from MMU-500 TRM.

    Address width

    The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address width is 48 bits and the width of the AC address

    bus…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does ARM have a time counter mechanism?

    Cyberman Wu
    Cyberman Wu

    Say, like Time Stamp Counter of x86, or Time Base of PowerPC, which can used to

    do some performance profiling.

    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • I am very new to ARM, still understanding the terminologies. What is the difference b/w the Cortex family and the x-gene?

    Moix
    Moix

    Where can i get a list of all these family of ARM processors and their differences

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Minimum MMU table size on ARMv8 to map 4GB memory space, in AArch64 mode

    yifanfeng
    yifanfeng

    On ARMv7 Cortex-A8/9/7, to map 4GB memory space, the minimum MMU table size is 16 KB(section mapping). Any possible to map 4 GB memory space with 16 KB MMU table, on ARMv8, AArch64 mode?

    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • where can I find the detailed explanation of ARM PMU events?

    alexamy
    alexamy

    Two questions:

    1. Where can I find the detailed explanation of ARM PMU events?

    2. How to know the stall cycles for e.g. icache miss etc.?

    Thanks.


    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • A strange problem in porting secure os in v8 secure EL1

    Steven Meng
    Steven Meng

    Hi, ARM experts:

        When we porting a secure os in 32bit mode in v8 secure EL1(our EL3 is running in AARCH 64bit mode), we got a strange problem:

        

        When start booting secure os in secure EL1, the bootstrap code…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv8 Secure EL1 problem

    Steven Meng
    Steven Meng

    Hi, arm experts,

    We want to use ARCH32 mode in secure EL1, I see some descriptions in ARMv8 Arch Reference Manual about Secure EL1 ARCH32 mode as follows:

    One is the VBAR(secure), it is mapped to  VBAR_EL3, the other is SCTLR (secure), it is mapped to …

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to schedule Secure/Normal kernels in TrustZone implementation?

    Kaiyuan
    Kaiyuan

    I read TZ whitepaper. TZ's software architecture includes normal OS, secure OS, and a monitor that manages switching between two OS. The notion is clear. But how to implement them confuses me.

    Running and managing two kernels on a SoC needs mechanism…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to use those crypto extension to write asm code?

    YaoCui
    YaoCui

    Now I use DS5 to develop an assembly crypto code, instructions like AESE are used in my code, after assign the CPU = 8-A.64.crypto, the code could be built, but when i debug the code in

    the FVP VE_AEMv8x1, the program crash, do anybody now how to use instructions…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • no C bit in SMMU_CBn_SCTLR

    Jerry
    Jerry

    I am reading SMMU spec V2.0, and wondering why no C bit in SMMU_CBn_SCTLR. There is M bit in it.


    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What will be happened if I insert a store instruction behind a LDREX instruction for accessing the same address?

    Jay.Dong
    Jay.Dong

    There is a system with two CPU,for example,cpuA and cpuB. Firstly, cpuA issue a LDREX for accessing the address A,and cpuB issued a STORE for writing the address A. If CPUA send a STREX for writing the address A after the Store issued by cpuB。 I notice…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Bus error while executing ARMv8 TLB instruction

    armdev
    armdev

    Hi,

    I am facing "Bus error on memory operation" while executing below instruction while invalidating and flushing the TLB.

    I am not able to understand what is the reason for "Bus error" as it is a TLB operation instruction ?  Also what Bus error…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • In ARM7 and ARM9 PC=current + 8, but in the cortex-A7(8-stage pipeline) the PC is also the same value(PC=current +8), how does this work?

    Kun.Niu
    Kun.Niu

    In ARM7 and ARM9 PC=current + 8, but in the cortex-A7(8-stage pipeline) the PC is also the same value(PC=current +8), how does this work?

    I think the cortex-A7 has 8-stage pipeline, the PC value is also current+8(this is back-forward for old design), but…

    • Answered
    • over 5 years ago
    • Processors
    • Classic processors forum
  • View related content from anywhere
  • More
  • Cancel
<>