I would like to know if TrustZone will ever be implemented on Cortex R:
I was able to find in your documentation that:
“TrustZone technology for ARMv8-M is also different from the virtualization approach as supported in the ARMv8-R architecture.…
I would like to know if TrustZone will ever be implemented on Cortex R:
I was able to find in your documentation that:
“TrustZone technology for ARMv8-M is also different from the virtualization approach as supported in the ARMv8-R architecture.…
I have ARM9E very well optimized code. If I run the same piece of code, how much of optimization/performance improvement can be seen on Cortex R4? Does anybody has benchmarking results between ARM9E and Cortex R4?
Hello,
What is the purpose of the RSDIS (Return Stack DISable) bit in ACTLR ?
What would be the consequence on code execution if set DISable ?
Is the software able to write this bit ?
Thanks for help
Hello All,
I am integrating CAN stack, on Spansion S6J3xx series.
I have configured Main clock as Input frequency, configured CAN transceiver IC and called CclPowerOnInit().
Now calling CanTransmit(X_TxHandle), function in a 100ms task, but still no signal…
Hi All,
In R4 trm, there are some words about low interrupt latency. I have a question about it.
" Low interrupt latency
On receipt of an interrupt, the processor abandons any pending restartable memory operations.
Restartable memory operations…
Dear Arm community,
is there any real-time application to demonstrate the R5-lock step feature.
other than Error injection in to the test register ?
Thanks,
Ravinder Are
Hi Experts,
Is there any application note on the Cortex R4 to R5 differences and what are all the special features R5 possess ?
Hi Experts,
What is the use case of split/lock configuration in the Application processors ?
Why does Cortex-R kernel only support Thumb-2?
Is this attribute has some advantages to the real-time response time?
According to the ARM spec (ARM DDI 0460D section 8.4.4):
As I know, Cortex-R5MP supports lock-step mode and every output from two cores will be compared in this mode.
I'm curious about the handling of Interrupt Service Routine during the lock-step mode.
When these two cores share same interrupt input, how can…
Hi all,
I need help for to convert logic in following way:
if 1st bit set in (00000000000000000000000000001) i can get 1
f 1st bit set in (00000000000000000000000000100) i can get 2
f 1st bit set in (00000000000000000100000000000) i can get 11
........…
Hi all,
It was nice experience working with NXP with my favorite S32K1XX series having ARM Cotex M-4 and M-0+.
Now i switched to BCM895XX series with ARM Cotex R-4 having VIC for interrupt contolling.
I am working with controller having ARM cortex R-4…
Hello,
I am trying to execute code which has two vector tables/ images, when making the transition from high vector 0xFFFF0000 to table in low 0x0
I am currently considering Cortex-R series processor
which has VINITH , and SCTLR as involved registers in…
Hello,
I'm trying to find the proper way to disable PFU / instruction pre-fetch on an R4. System control register bit 12 might do the job, but it's not clear to me:
Determines if instructions can be cached at any available cache level:
0 = instruction…
This may sound stupid but I'd like to confirm my understanding of the processor behavior, in the event of a Data Abort. Section 3.8 of the Cortex R5 Techincal Reference Manual explains the Exception handling by the processor and my current understanding…
Using Cortex-R5F, I would like to get the contents of the 4-entry call-return stack (i.e. get the addresses). Is this possible through some indirect manner?
The goal here is to have the knowlege of the call tree above the current execution point (backtrace…
Hi Experts,
I need to run freeRTOS on processor having Arm cortex -R52 series .I have download source code from freertos.org for ARM_CR5 series.Does all port file will be compatible for R52 processor also and if no what are the changes we need to make…
Hi Expert,
I am using processor with R52 Arm cortex and I need to change hypervisor mode to system mode during run time i.e EL2 to EL1.Is there any instruction to change this?
Thanks In Advance.
Hi,
I have a Cortex-R5F core in which integration register value CPACR.ASEDIS = 1 and CPACR.D32DIS = 1m which says Advanced SIMD is not available. However, in ARM Cortex-R5F Technical Reference Manual revision r1p2, §2.1.2 "ARM architecture", it says…
The Cortex-R5 has a single AXI peripheral physical bus which is divided into a LLPP Normal AXI interface and an LLPP Virtual AXI interface. The TRM document also explains that ordering is disconnected between these 2 interfaces. Fine.
However, I am not…