• TrustZone in CortexR

    Poz1
    Poz1

    I would like to know if TrustZone will ever be implemented on Cortex R:

    I was able to find in your documentation that:

    “TrustZone technology for ARMv8-M is also different from the virtualization approach as supported in the ARMv8-R architecture.…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-R / R-Profile forum
  • Cortex-R4: Need a explanation for dual-issue restriction

    Jason Lee
    Jason Lee

    Hello,

    The following table is extracted from the Cortex-R4 whitepaper:

    Untitled.png

    Could someone help me to explain that question:

    My concern is that Cortex-R4 can take MOV as first instruction, ADD as second instruction to a dual-issue pair in C category means that…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Cortex R4 versus ARM9E

    Sridhar Artham
    Sridhar Artham

    I have ARM9E very well optimized code. If I run the same piece of code, how much of optimization/performance improvement can be seen on Cortex R4? Does anybody has benchmarking results between ARM9E and Cortex R4?

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • purpose of RSDIS in ACTLR ?

    Sylvain
    Sylvain

    Hello,

    What is the purpose of the RSDIS (Return Stack DISable) bit in ACTLR ?

    What would be the consequence on code execution if set DISable ?

    Is the software able to write this bit ?

    Thanks for help

    • over 4 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • CAN Stack Integration for ARM cortex R5F

    Prateek Nandi
    Prateek Nandi

    Hello All,

    I am integrating CAN stack, on Spansion S6J3xx series.

    I have configured Main clock as Input frequency, configured CAN transceiver IC and called CclPowerOnInit().

    Now calling CanTransmit(X_TxHandle), function in a 100ms task, but still no signal…

    • over 4 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • What does "low interrupt latency" means

    Patrick
    Patrick

    Hi All,

    In R4 trm, there are some words about low interrupt latency. I have a question about it.

    "   Low interrupt latency

    On receipt of an interrupt, the processor abandons any pending restartable memory operations.

    Restartable memory operations…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • ARM Cortex-R5 based Lock-step feature demonstration real time application?

    Ravinder
    Ravinder

    Dear Arm community,


    is there any real-time application to demonstrate the R5-lock step feature.

    other than Error injection in to the test register ?

    Thanks,

    Ravinder Are

    • over 5 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Application note on R4 and R5 differences

    techguyz
    techguyz

    Hi Experts,

    Is there any application note on the Cortex R4 to R5 differences and what are all the special features R5 possess ?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Usage of Split/Lock Configuration

    techguyz
    techguyz

    Hi Experts,

    What is the use case of split/lock configuration in the Application processors ?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • What's the difference between ETM and Debug?

    Kun.Niu
    Kun.Niu

    In the ARM core such as cortex-R4, it has ETM and Debug so I want ask What's the difference between ETM and Debug?

    CR4_diagram.PNG
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • In Cortex-R4, the interrupt from which part to send to the core?

    Kun.Niu
    Kun.Niu

    In Cortex-R4, the interrupt from which part to send to the core?

    In the bellow diagram, Cortex-R4 doesn't give an interrupt input port, so I want ask the interrupt connect to the Cortex-R4 kernel from which part?

    CR4_diagram.PNG
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Why does Cortex-R kernel only support Thumb-2?

    Kun.Niu
    Kun.Niu

    Why does Cortex-R kernel only support Thumb-2?

    Is this attribute has some advantages to the real-time response time?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Why does Cortex-R only support most two cores?

    Kun.Niu
    Kun.Niu

    Why does Cortex-R only support most two cores?

    only_two_core.PNG
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • TCM arbitration hazard: Considerations for Firmware

    c0deface
    c0deface

    According to the ARM spec (ARM DDI 0460D section 8.4.4):

    TCM arbitration
    Each TCM port receives requests from the LSU, PFU, and AXI slave. In most cases, the LSU
    has the highest priority, followed by the PFU, with the AXI slave having lowest priority…
    • over 1 year ago
    • Processors
    • Cortex-R / R-Profile forum
  • Is that possible for Cortex-R5's dual-core to handle interrupt during lock-step mode?

    AJ
    AJ

    As I know, Cortex-R5MP supports lock-step mode and every output from two cores will be compared in this mode.

    I'm curious about the handling of Interrupt Service Routine during the lock-step mode.

    When these two cores share same interrupt input, how can…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Bit scan Instruction ARM cortex R4

    Yash
    Yash

    Hi all,

    I need help for to convert logic in following way:

    if 1st bit set in  (00000000000000000000000000001)  i can get 1

    f 1st bit set in  (00000000000000000000000000100)  i can get 2

    f 1st bit set in  (00000000000000000100000000000)  i can get 11

    ........…

    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Very Urgent :VIC in ARM Cortex R4

    Yash
    Yash

    Hi all,

    It was nice experience working with NXP with my favorite S32K1XX series having ARM Cotex M-4 and M-0+.

     Now i switched to BCM895XX series with ARM Cotex R-4 having VIC for interrupt contolling.

     I am working with controller having ARM cortex R-4…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Right way to jump to New Vector Table without Reset

    ZXCFD
    ZXCFD

    Hello,

    I am trying to execute code which has two vector tables/ images, when making the transition from high vector 0xFFFF0000  to table in low 0x0 

    I am currently considering Cortex-R series processor

    which has VINITH , and SCTLR as involved registers in…

    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Disabling PFU / instruction pre-fetch on Cortex-R4?

    N. Gineer
    N. Gineer

    Hello,

    I'm trying to find the proper way to disable PFU / instruction pre-fetch on an R4. System control register bit 12 might do the job, but it's not clear to me:

    Determines if instructions can be cached at any available cache level:
    0 = instruction…

    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Cortex-R5: Data abort handling

    c0deface
    c0deface

    This may sound stupid but I'd like to confirm my understanding of the processor behavior, in the event of a Data Abort. Section 3.8 of the Cortex R5 Techincal Reference Manual explains the Exception handling by the processor and my current understanding…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Can we inspect contents of the return stack to get the call tree?

    Etienne Alepins
    Etienne Alepins

    Using Cortex-R5F, I would like to get the contents of the 4-entry call-return stack (i.e. get the addresses). Is this possible through some indirect manner?

    The goal here is to have the knowlege of the call tree above the current execution point (backtrace…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Porting FreeRTOS On R-52 Cortex

    Himanshu Khanna
    Himanshu Khanna

    Hi Experts,

    I need to run freeRTOS on processor having Arm cortex -R52 series .I have download source code from freertos.org for ARM_CR5 series.Does all port file will be compatible for R52 processor also and if no what are the changes we need to make…

    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Hypervisor Mode to System Mode in R52 cortex

    Himanshu Khanna
    Himanshu Khanna

    Hi Expert,

    I am using processor with R52 Arm cortex and I need to change  hypervisor mode to system mode during run time i.e EL2 to EL1.Is there any instruction to change this?

    Thanks In Advance.

    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • Is Advanced-SIMD supported in Cortex-R5F?

    Etienne Alepins
    Etienne Alepins

    Hi,

    I have a Cortex-R5F core in which integration register value CPACR.ASEDIS = 1 and CPACR.D32DIS = 1m which says Advanced SIMD is not available. However, in ARM Cortex-R5F Technical Reference Manual revision r1p2, §2.1.2 "ARM architecture", it says…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
  • When is Cortex-R5 Virtual Peripheral AXI bus used?

    Etienne Alepins
    Etienne Alepins

    The Cortex-R5 has a single AXI peripheral physical bus which is divided into a LLPP Normal AXI interface and an LLPP Virtual AXI interface. The TRM document also explains that ordering is disconnected between these 2 interfaces. Fine.

    However, I am not…

    • over 2 years ago
    • Processors
    • Cortex-R / R-Profile forum
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