• Cortex M4 L1 data cache policy

    nothing
    nothing

    I have some confusions about the difference between write back + write allocate and write back + write no allocate on Cortex CM4.

    As my original understanding:

    • For write back with write allocate:
      • If write-address isn't cache hinted yet, cache line…
    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • IAR Compilation error

    myself_subhash
    myself_subhash

    Hi 

    I am compiling below assembly language code for ARM Cortex M4 using IAR Workbench and getting error, could some one help me on this. calling BadWebConfig_Txt from C code.

    #define code_ADDRESS(a) ((a)>>24 & 0ffH,(a)>>16 & 0ffH,(a)>>8 & 0ffH,(a) & 0ffH…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • RNG (Random) on Cortex-M4

    Amir
    Amir

    Many implementations on Cortex requires true random number generation.

    It is very common to use seed based on the tick counter and then rand() function which is "just" a constant fixed known function.

    However, if after each reset, application…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • CM4: Is DAP immune to MPU protections?

    SysTom
    SysTom

    Can the DAP cause exceptions by performing illegal instruction in spaces protected by MPU or is it immune?

    Trying my hand at setting up MPU but I cannot get it to fire - thought it might not be possible with DAP.

    Thanks, Tom

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Problem with SWO when debugger not connected

    ciaranmac
    ciaranmac

    Hi,

    I have configured my M4 based CC3200 from TI to output printf via ITM (all uarts used). Works great as long as the debugger is connected. But when I boot up with no debugger it streams out unrecognisable packets. The normal packets are one header…

    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Where to find the execution cycles of Cortex m7 instruction

    tyskin
    tyskin

    for Cortex-M0, M3 and M4, I can find the execution time in their Technical Reference Manual > Programmers Model > Instruction set summary 里面查看

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0432c/CHDCICDF.html

    but for M7 It said that…

    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • CM4: Can processor halt itself by writing DHCSR

    SysTom
    SysTom

    Hello,

    As part of my diagnostic regime I wanted the diag to halt when completed.  It doesn't seem like it can.  It seems to keep running when I 

      CoreDebug->DHCSR = (0xA05FUL << CoreDebug_DHCSR_DBGKEY_Pos) |
                         CoreDebug_DHCSR_C_HALT_Msk…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • When will be the Release of "The Definitive Guide to Cortex M7" ??

    harshan
    harshan

    Hi Sir,

    may be the title of this question looks fun, but i am eagerly waiting for your next book "The Definitive Guide to Cortex M7" are you working on this book?? When could i Expect this book

    Thanks and Regards,

    Harshan.

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Current Variation due to Functional Unit activation or deactivation

    HimanshuDoshi19
    HimanshuDoshi19

    Hello to all,

    I would like to measure the current variation due to Functional Unit activation and deactivation. Can anyone help me out with the assembly program or the code through which I can measure this? I am using LPCXpresso 54114 board(ARM Cortex…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Variation in the current consumption due to memory address and offset value?

    HimanshuDoshi19
    HimanshuDoshi19

    Hello to all,

     

    I am trying to figure out the variation in current consumption as well as in clock cycles due to different memory regions and different offsets. During various experiments, I have found the following results:

     

    LDR R4,[R1,#0x0]  (R1 = 0x00000000…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to get to know the exact instruction address or find the instruction address for least current consumption?

    HimanshuDoshi19
    HimanshuDoshi19

    Hello to all,

    In order to measure the current variation due to instruction address location. I filled the memory with NOP instructions and tried to observe the variation in the current consumption due to change in the instruction address, although the…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Difference in the current consumption for different register place for few instructions

    HimanshuDoshi19
    HimanshuDoshi19

    Hello to all,

    While working on different assembly instructions, I have come across a very different problem of the register's place. For example: 

    SBC r11,r7,r11 : 3.0217mAmps

    but 

    SBC r11,r7,r7 : 2.7477mAmps

    Similarly, for ORN and MVN also.

    For all…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Interface Cortex M4 and PSRAM with different power supply voltage

    DavidCavalheiro
    DavidCavalheiro

    Dear all,

    could you please tell me if it is possible to interface a Cortex M4 (3.3V) with a PSRAM (1.8V) directly or do I have to add a logic level (Voltage Translation) between both?
    With kind regards,
    David

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Forced Hardfault (INVPC) Exception Error

    Lokesh
    Lokesh

    Using ARM coretx-M chip set

    Getting random  INVPC hard fault exception error, while running iperf tool for measuring n/w throughput.

    Hard fault reg: 0x40000000

    xPSR: 0x01000000

    PRIMASK: 0x00000001

    CONTROL: 0x00000000

    Please help to find the possible root…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • MFLOPS of M4F

    Timm Hinrichs
    Timm Hinrichs

    Hi,

    we are operating the M4F with 160MHz and we would like the know the MFLOPS we can achieve with this configuration.

    Regards,

    Timm

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cannot init heap using scatter file and C++ startup (Cortex-M4)

    Dron
    Dron

    Hello,

    I need help with heap initialization using scatter file and C++ startup.

    MCU is STM32F407VGT6 (Cortex-M4).

    Compiler is ARM Compiler 6.7, C++14.

    The problem is that all variables which I create dinamically on the heap have wrong addresses. My HEAP…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Change Vector Table in cortex M4 in a persistent way

    EA8
    EA8

    Hello,

    I need to change the Vector Table but I need it to be persistent through a reset, what I'm trying to do is set a vector table duplicate as a safety measurement for reprogramming the original vector table.

    So far I being playing with the VTOR…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • What happens to upper half of 32-bit data bus when reading 16-bit chip?

    Pszemol
    Pszemol

    Hi guys, I am interested in exploring a scenario when Cortex M4 cpu performs a 16-bit static memory read when 32-bit memory is actually on the board.

    The 16-bit memory chip is connected to lower half of the data bus, signals D0..D15 and there are two…

    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • DMB, DSB, ISB on Cortex M3,M4,M7 Single Core parts

    Trampas
    Trampas

    I have been reading through the ARM documentation on memory and instruction barriers. 

    I have read that the single core ARMv7-M parts do not reorder instructions, as such the DSB and ISB are not needed, is this correct? 

    I have also read the same about…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Looking for typical max frequency for Cortex-M CPUs

    ahming
    ahming

    I'm looking for information on the typical max frequency (or typical frequency range) for the Cortex-M cores, in 40nm. Is there any documentation on that? Thanks.

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • When an exception is taken into account

    Karolis
    Karolis

    Hi

    Related to ARMv7-M architecture:

    I am searching through all infocenter documents but still cannot find anything and answer this question: "When an exception is taken into account?" I mean, are exceptions only serviced after the current instruction…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to properly measure sleep time with DWT?

    Tilen
    Tilen

    Hello everyone,

    I need to measure sleep time of my Cortex-M4 processor (STM32F4xx).

    I looked at DWT where I also use normal tick counter and I enabled SLEEPCNT counter.

    However, I noticed that it is 8-bit register with event generation support.

    Now, there…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Prefetch Abort in Cortex M processors

    kmdinesh
    kmdinesh

    Hi,

    We are currently working with Cortex M4 processor and previously we worked with Cortex R5 processor. As part of our project requirement, we need to detect "prefetch abort" exception and to identify the corresponding address. In Cortex R5, we are taking…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • A panic function to halt the processor in low-power sleep using WFI?

    Alexei
    Alexei

    As part of fault detection / debugging, it's useful to have a panic() function that halts the processor.

    It is easy enough to disable interrupts and put the processor in an infinite busy loop (while (1)). However, that burns power, and I am looking…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • DWT

    Gabor M.
    Gabor M.

    Hello,

    I use DWT in Cortex-M4 to catch instructions that write or read memory contents and the problem is it doesn't stop immediately where I expect, it stops after 2-3 instruction later than where it should and the contents of registers are overwritten…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
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