• Changing prio of running IRQ triggers hardfault

    Vinci
    Vinci

    Hello

    I've a question regarding the NVIC on Cortex M4 devices. Up until today I was under the impression that changing the priorities of a running interrupt isn't an issue in the ARMv7-M architecture, but the following pseudo-code snippet keeps triggering…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Saving processor state for power-down and resume

    Andrew Heale
    Andrew Heale

    I'm working on a SoC that can power-off the ARM (Cortex-M4) while retaining the system RAM, and I'm interested in saving the processor state then restoring it when the ARM is restarted.  So prior to power-off the software would save all necessary…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to test atomic access implemented with Load Store Exclusive Assembly (LDREX / STREX)

    Clemens Grünberger
    Clemens Grünberger

    Hi there,

    i have several inline assembly functions wrapped in C.

    They implement atomic / read-modfy-write style

    • Compare And Swap
    • Increment
    • Decrement
    • Lock Semaphore

    Creating a  good case Test i got done.

    But now i am struggling to produce a reliable…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Hardfault error on callback

    Indy
    Indy

    Hi,

    I'm trying to figure out why a registered callback function is failing.

    C:
    socket->cb.socket(socket_idx, 0);

    ASM:
    It fails at:

    00415B88   ldr    r3, [r4, #60]        
    00415B8A   mov    r1, r11        
    00415B8C   mov    r0, r6        
    -> 00415B8E   blx    r3        
    00415B90   b    #-676…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • hardfault error

    Indy
    Indy

    Hi!

    I'm getting hard fault error and I cannot figure out why. Can anybody point me to the right direction?

    The architecture is Cortex-M4 with stack size of 0x3000.

    It doesn't seem to be stack overflow as I raised it to the double size and still the…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Unable to Download Code to Controller

    ShivasWorld
    ShivasWorld

    Hello All, 

    We have custom PCB having ATSAME54P20A microcontroller. Suddenly today I started getting CPU Status - LOCKUP error and I am unable to download the code to the microcontroller.  Before, that I am able to download the code to controller but it…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Low-Level NOR Chip Interfacing and Embedded File System (EFS) Resources

    japolo
    japolo

    Hello all, 

    I am currently working on a project that requires me to interface with a single external NOR flash chip from Cypress (S29GL064880TFV030), the microcontroller that I'm working with is a STM32F407ZGT7 (LFQP144 Pin Package). I've read through…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Does "LDRD" instruction cause "UNDEFINSTR" error on Cortex-M4?

    Gavin Li
    Gavin Li

    Dear Experts,

        I'm working on a freertos project which is running at Cortex-M4 and I'm being troubled by a problme - hard fault.

    The following is my debugging process:

        I dump the registers in the stack when the hardfault happens.

     [Hard fault…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Audio mixing efficiently and hard realtime requirment

    Manojkumar Subramaniam
    Manojkumar Subramaniam

    warm greetings, I would want to know how capable is ARM M4 in handling up to 4 channel audio mixing of 24bits 44khz audio.

    Audio fetching will be from Sd card system with FAT32 FS, QSPI to have high speed fetch. and once the audio is mixed it will stream…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex-M: Does the event register only get set when an IRQ changes from not pending to pending?

    m.wagner
    m.wagner

    I recently had a race-condition in an application on a Cortex-M4 microcontroller, because I used a wrong order of __SEV() and __WFE() instructions to put my chip to sleep. While debugging this issue, I wondered when exactly the event register does get…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • semihosting on 4.9.3 q2 2015

    Neo
    Neo

    Hi,

    I had a small program which was  run on a CM4 and it was using semihosting.

    The code works fine wiht 4.9.3 q1 2015.

    When I picked the latest 4.9.3 q2 2015  the  program fails to run.

    It cannot allocate memory from heap.

    So I tried a sample…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Suggestion on suitable arm processor

    Ma Seet Ting
    Ma Seet Ting

    Hi all. Nice to meet you all and glad that I have a chance to join this group=)
    Recently, I will do my final year project with the title of "Smart Home Control Using Brain Wave". Yet, I am not really sure on which arm that I should choose><…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Question on clock gating for AHB -lite bus matrix for CM4 based system

    Dhaval
    Dhaval

    Joseph,

    We are using CM4 and AHB -lite bus components from ARM system development kit. We have 3 different AHB masters in the system, including CM4.

    I am wondering if we could use HTRANS from each master and combined that information to gate the AHB-lite…

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Question about bit-banding for Tiva M4 core

    Robert
    Robert

    Hi,

    I read example projects of Tiva-C 1294. There are many similar uses '    GPIOPinWrite(GPIO_PORTH_BASE, GPIO_PIN_2, GPIO_PIN_2);'

    The prototype is :

    extern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val)…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • M4/M0 dual core application. M0 fails to start

    Bo Mellberg
    Bo Mellberg

    Hello everyone,

    I have an LPC4337 running uCLinux. I'm trying to get code to run in the M0 in parallell.

    I load the code to 0x10080000, set the M0APPMEMMAP to 0x10080000, release the M0APP Reset and nothing happens. I have to reset the M0-core using…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • "Dormant Mode" for Cortex M3/M4

    Steven Dennis
    Steven Dennis

    Hi,

    We are interested in minimizing startup time from deep sleep mode.

    Some of the older ARM cores implement a dormant mode whereby the CPU core context (state) is written to RAM prior powering it down, and then then restored after the CPU core  is powered…

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Problem running copied code into flash

    Luís Rafael dos Santos Afonso
    Luís Rafael dos Santos Afonso

    Hi everyone,

    So I have a question.

    I have a ARM-M4 and for what I can tell this has both ARM and Thumb assembly. Meaning sometimes it interprets a 32 bit instruction as 2 16bit ones, some of the times.

    How does that work? How does it know how to go about…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Can anyone tell me where I can download the latest Cortex M4 Technical Reference Manual

    Peter Grey
    Peter Grey

    Where are the Technical Reference manuals located?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Do ARM processors have power good signal to check quality of incoming power?

    nirmalaranawat
    nirmalaranawat

    I am working on one of TI's SOC using ARM M-4 processor. I was wondering if the ARM processors have any Power Good signal which can be used in software stack to control flow of application.

    Or storing some data before power goes out completely.

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Does anyone use assembler only with an ARM MCU?

    Peter Grey
    Peter Grey

    I have only used assembler when working with MCU's. I can follow a C program but have not used it in any commercial product. Can anyone suggest a development platform to start off learning the ARM and C? I would probably work on a Cortex M4F as a start…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • about tail chaning of Cortex-M0

    下田敏郎
    下田敏郎

    Hello.

    I'm studying about the tail chaining of Cortex-M0.

    Is it same as Cortex-M3 or M4?

    Best regards.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Bit-banding in SRAM region (Cortex-M4)

    Matic
    Matic

    Hi.

    I would like to use bit-banding feature in SRAM, but don't know exactly how to implement it with C. I already use bit-banding in peripheral region with this kind of macro:

    #define BITBAND_PERI_REF        0x40000000…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • ARM CM4 FPU execption

    Anuj
    Anuj

    I am looking for FPU exception generation code. If some one share, or suggest some document for the same.

    Regards

    Anuj

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • cmsis NVIC question.

    Setianian
    Setianian

    Hello, Everybody. I have several questions.

    1. Please See the NVIC_Type structure. I don't understand about why ISER,ICER,ISPR and ICPR use size of array 1( I think It can use just __IO uint32_t ISER; ), and what does RESERVEDs do???

    2. I would like…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Race condition between wake up event and WFI on Cortex-M3/M4

    neo
    neo

    When I read below thread in arm forum, I still not clear which one is the safety way.

    Cortex-M4: guaranteed wakeup from WFI?

    There're two solutions mentioned above, using WFE instead of WFI, and swap __WFI() and __enable_irq().

    I can understand WFE…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
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