• How do I implement the cortex M3 Boot ROM code?

    ele
    ele

    Dear All,
    As I know, In Cortex M3, was implemented such as the B_ROM, I_RAM, D_RAM .
    and Basically, Cortex M3 is consist with internal memory ROM and SRAM.
    In Boot sequence, first of all, IROM code load BL1 code into the SRAM.
    So I want to know especially…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Forced Hardfault (INVPC) Exception Error

    Lokesh
    Lokesh

    Using ARM coretx-M chip set

    Getting random  INVPC hard fault exception error, while running iperf tool for measuring n/w throughput.

    Hard fault reg: 0x40000000

    xPSR: 0x01000000

    PRIMASK: 0x00000001

    CONTROL: 0x00000000

    Please help to find the possible root…

    • Answered
    • over 2 years ago
    • Processors
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  • How to interface TFT display with lpc1768

    chinna@422
    chinna@422

    I am new to lpc1768, i facing problem in how to start interfacing TFT mr024-9325-51p 2.4" DISPLAY . please help me in that. if anybody provide example code that will help me alot. thank you.

    • Answered
    • over 2 years ago
    • Processors
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  • Cortex M3, PrimeCell uDMAC bus arbitration

    acoad
    acoad

    Hi,

    This is in the context of the Cortex-M3 and PrimeCell uDMAC as implemented in the Texas Instruments CC2640R2F Bluetooth controller (I have gone through the TI support forums for this question but it seems that this is fully within the ARM IP domain…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • DMB, DSB, ISB on Cortex M3,M4,M7 Single Core parts

    Trampas
    Trampas

    I have been reading through the ARM documentation on memory and instruction barriers. 

    I have read that the single core ARMv7-M parts do not reorder instructions, as such the DSB and ISB are not needed, is this correct? 

    I have also read the same about…

    • Answered
    • over 2 years ago
    • Processors
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  • Interruptible Instructions on Cortex-M4

    praffeck
    praffeck

    The ARM Cortex-M4 Processor Technical Reference Manual states:

    To minimize interrupt latency, the processor abandons any divide instruction to take any pending interrupt. On return from the interrupt handler, the processor restarts the divide instruction…

    • Answered
    • over 2 years ago
    • Processors
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  • CortexM3 : Issue when image start address is other than 0x0

    Khushi
    Khushi

    I have a very simple CortexM3 based virtual platform example as below

    The amba_pv_m2 is connected to a memory in the top. The BusDecoder master port address range is 0x0-0x3FFFFFFF

    I have the following C program

    #include <stdio.h>

    int main(int…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • When an exception is taken into account

    Karolis
    Karolis

    Hi

    Related to ARMv7-M architecture:

    I am searching through all infocenter documents but still cannot find anything and answer this question: "When an exception is taken into account?" I mean, are exceptions only serviced after the current instruction…

    • Answered
    • over 2 years ago
    • Processors
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  • how dose the PC run to startup.s when the mcu reset

    rookie enginner
    rookie enginner

    Hi,dear enginner:

        i want to know how the PC run to startup.s when mcu reset?

       The Definitive Guide to the ARM Cortex-M3 says address 0x00000000 is MSP‘,address 0x00000004 is ResetVector.

       But when I look at STM32F767, I find that 0x00000000 and…

    • Answered
    • over 1 year ago
    • Processors
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  • M0+ Stack Pointer (PSP/MSP) Clarification

    Sean Dunlevy
    Sean Dunlevy

    Background

     I'm working part-time on a Cortex M0+ based SoC converting a very processor-intensive section of C++ code (inner-loop executed 10s of 1000s of times a second & compiles to over 400 instructions using GNU O3) and after almost 3 months of work…

    • Answered
    • over 1 year ago
    • Processors
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  • Access ETM without using a debug kit

    Lorenzo_UR
    Lorenzo_UR

    Hi

    i'm using Nucleo board F401RE.

    i want to access to ETM with code.

    i'm using IAR Embedded Workbench

    My code:

    #define ETM_CR 0xE0041000 // Address of ETM_CR

    #define ETM_LAR 0xE0041FB0 // Address of  ETM_LAR

    #define UNLOCK 0xC5ACCE55 // Value…

    • over 2 years ago
    • Processors
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  • Help with programming STM32F103RCT6 board.

    makiyoung
    makiyoung

    I have bought  this Cortex M3 board. Now I want to program it through jtag.

    So I bought this wire. By using the USB to serial interface of my linux machine, I want to program the board.

    I went to read the data sheet of board here[1]. In section 2.3.29…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Program ARM-device from Linux

    yahniukov
    yahniukov

    Hello everyone!

    I want to buy STM32F103C8T6 and my os is Ubuntu and I don't want to use IDEs. I already found the developer's tools - GNU Arm Embedded Toolchain, but have the question - there is a suitable linux software to program ARM devices…

    • Answered
    • over 3 years ago
    • Processors
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  • instructions fetch

    lyk
    lyk

    Hello, when I use stm32f103xx, I am confused of  one of the boot modes it supported. One of  the boot modes is booting from embedded SRAM while the I-BUS of Cortex-M3 is connected to FLASH only . When boots from SRAM,  how Cortex-M3 fetches instructions…

    • Answered
    • over 3 years ago
    • Processors
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  • Hard Faults and MemManage Faults in Cortex m3/m4

    Muzahir
    Muzahir

    I wrote a simple program, where I am writing to an illegal memory location. Writing in an illegal Memory location generates a MemManage fault. And if MemManage is not enabled, HardFault in generated. But in my case hardfault is also not triggering.

    Here…

    • over 3 years ago
    • Processors
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  • INVPC Hard fault exception error

    DrWhom DrWhom
    DrWhom DrWhom
    Note: This was originally posted on 16th July 2009 at http://forums.arm.com

    Using and Arm Cortex M3, the application that is running sometimes will generate a hard fault and deciphering the CFSR register tells me that the following user fault is triggerred…
    • Answered
    • over 7 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • the means of tail-chaining of interrupts

    xiasxian
    xiasxian

    hellow

         I am reading the book  “Cortex  -M3 Embedded Software Development” on page of 3,chapter 1.1 Nested Vectored Interrupt Controller (NVIC),

    i don not understand  the means of tail-chaining of interrupts .In the sentence of  "The NVIC also…

    • over 2 years ago
    • Processors
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  • i2c LPC1788 interface with raspberry pi3

    Jvis
    Jvis

    Greetings ARM peoples

    I am trying to interface LPC1788 with Raspberry Pi3 through I2C.

    Raspberry Pi will be master and LPC will be slave (More LPC slaves have to be added in future)

    Raspberry will send set of data to LPC and LPC will generted output for…

    • Answered
    • over 2 years ago
    • Processors
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  • NVIC and ARM asm

    martin
    martin

    Cannot configure interupts of TIM6 on stm32f103 board

    Does my NVIC configuration wrong?

    Code:

    @ stm32f103 timer & interrupt test by laper_s (from 2019-02-02)
    
    .thumb
    .cpu cortex-m3
    .syntax unified
    
    .word   0x20005000
    .word   start + 1
    
    b   start…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • CortexM3

    Khushi
    Khushi

    I have a very simple CortexM3 based virtual platform example as below

    The amba_pv_m2 is connected to a memory in the top. The BusDecoder master port address range is 0x0-0x3FFFFFFF

    I have the following C program

    #include <stdio.h>

    int main(int…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • LDREX/STREX on the M3,M4,M7

    Trampas
    Trampas

    Doing some research of the LDREX and STREX it appears that the exclusivity address range for these instructions on the M3,M4,M7 is the entire memory space. Hence you can only use the LDREX/STREX with one address.   Does this not limit you to one Mutex …

    • Answered
    • over 2 years ago
    • Processors
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  • Does Documents have release Notes or update history?

    MR.Smile
    MR.Smile

    The G version has 410 pages!

    However, the H version reduce to 133 pages!

    It's like a big lost! 

    what's difference between the older and newer version?

    I think it's the ARM job to tell the difference. It's hard and wasting time for the user to…

    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Does Cortex-M3/M4 continue with burst in response to ERROR?

    MSaif
    MSaif

    AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'.
    What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in response to ERROR in some special cases?

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Interrupt switching during Late Arrival- CortexM3

    Vartika Singh
    Vartika Singh

    In Cortex-M3 manual, it is mentioned that during Late Arrival, when low-priority interrupt (LP) has already pushed 8 registers to Stack and high-priority interrupt (HP)occurs then, for (HP), we don't need to do any state saving. What does it mean by …

    • Answered
    • over 2 years ago
    • Processors
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  • How to start accessing the flash rom on Cortex-M3 design kit by JTAG?

    ele
    ele

    Hi,

    I'm trying to simulate which is accessing the flash rom on Cortex m3 design kit by JTAG?

    Is there any related test case or example?

    How to start accessing the flash rom on Cortex-M3 design kit by JTAG?

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
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