• Raising priority of PendSV within NVIC when PendSV pending

    Ramzyo
    Ramzyo

    Hi,

    I'm trying to understand the behavior of raising (lowering numerical priority) the priority of PendSV in the NVIC of a Cortex M4 or M7 when PendSV is already pending. Below are the cases I'm grappling with,

    1) High priority interrupt ISR is…

    • Answered
    • over 2 years ago
    • Processors
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  • CortexM3

    Khushi
    Khushi

    I have a very simple CortexM3 based virtual platform example as below

    The amba_pv_m2 is connected to a memory in the top. The BusDecoder master port address range is 0x0-0x3FFFFFFF

    I have the following C program

    #include <stdio.h>

    int main(int…

    • Answered
    • over 2 years ago
    • Processors
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  • CortexM3 : Issue when image start address is other than 0x0

    Khushi
    Khushi

    I have a very simple CortexM3 based virtual platform example as below

    The amba_pv_m2 is connected to a memory in the top. The BusDecoder master port address range is 0x0-0x3FFFFFFF

    I have the following C program

    #include <stdio.h>

    int main(int…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Number of Integer and Floating point execution units in M7

    Kallooran
    Kallooran

    Hi guys,

    I have 2 doubts.

    1) the number of integer and floating point execution units in cortex M7

    2) is the number of pipeline stages different for integer and FP 

    • Answered
    • over 2 years ago
    • Processors
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  • When an exception is taken into account

    Karolis
    Karolis

    Hi

    Related to ARMv7-M architecture:

    I am searching through all infocenter documents but still cannot find anything and answer this question: "When an exception is taken into account?" I mean, are exceptions only serviced after the current instruction…

    • Answered
    • over 2 years ago
    • Processors
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  • Which Arm processor to select?

    V.H.A.P
    V.H.A.P

    Currently I am working on a dynamometer project for analysing PMDC motor parameter to create a laboratory setup , so how should I proceed in the selection criteria of the processor for my project ,as I have to know the speed ,  torque, current, temperature…

    • Answered
    • over 2 years ago
    • Processors
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  • MIPS of Arm cortex m7

    shreyas@007
    shreyas@007

    Hi.

    I need the MIPS of cortex m7 processor. The results which I saw on wikipedia were in DMIPS. But i need it in MIPS only.

    Can someone help me with it?

    Thanks,

    Shreyas

    • over 2 years ago
    • Processors
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  • Cortex M0/M0+/M1 32-bit x 32-bit --->64-bit signed multiply

    Sean Dunlevy
    Sean Dunlevy

    I have been spent about 2 months trying to find a faster way of multiplying 2 32-bit numbers giving a 64-bit result. It is truly driving me mad because it FEELS like their is a faster solution. I should add that this example is for a 100% assembly-language…

    • Answered
    • over 2 years ago
    • Processors
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  • LDREX/STREX on the M3,M4,M7

    Trampas
    Trampas

    Doing some research of the LDREX and STREX it appears that the exclusivity address range for these instructions on the M3,M4,M7 is the entire memory space. Hence you can only use the LDREX/STREX with one address.   Does this not limit you to one Mutex …

    • Answered
    • over 2 years ago
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  • Why thumb code can only access r0-r7?

    Wenchuan2018
    Wenchuan2018

    Hi Sir,

    I want to know why thumb code can only access r0-r7, which described in ATPCS?

    Thanks and best regards,

    Wenchuan

    • Answered
    • over 2 years ago
    • Processors
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  • Cortex M7 DSP moving average UMAAL

    Mr_M_from_G
    Mr_M_from_G

    Hello,

    I am looking to do a moving average function using DSP instructions of ARM Cortex M7. Unfortunately I couldn't find a direct example. My goal is to have variables for

    - the sum

    - the new value

    - the oldest value

    Then the algorithm is sum =…

    • Answered
    • over 2 years ago
    • Processors
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  • How to properly measure sleep time with DWT?

    Tilen
    Tilen

    Hello everyone,

    I need to measure sleep time of my Cortex-M4 processor (STM32F4xx).

    I looked at DWT where I also use normal tick counter and I enabled SLEEPCNT counter.

    However, I noticed that it is 8-bit register with event generation support.

    Now, there…

    • Answered
    • over 5 years ago
    • Processors
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  • Prefetch Abort in Cortex M processors

    kmdinesh
    kmdinesh

    Hi,

    We are currently working with Cortex M4 processor and previously we worked with Cortex R5 processor. As part of our project requirement, we need to detect "prefetch abort" exception and to identify the corresponding address. In Cortex R5, we are taking…

    • Answered
    • over 2 years ago
    • Processors
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  • Measuring Cortex-M4 instruction clock cycle counts

    Dan Lewis
    Dan Lewis

    I'm trying to find a reliable method for measuring instruction clock cycles on the STM32F429 MCU that incorporates a Cortex-M4 processor. Part of the challenge is that although the core CPU has no cache, ST added their own proprietary ART Accelerator…

    • Answered
    • over 2 years ago
    • Processors
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  • A panic function to halt the processor in low-power sleep using WFI?

    Alexei
    Alexei

    As part of fault detection / debugging, it's useful to have a panic() function that halts the processor.

    It is easy enough to disable interrupts and put the processor in an infinite busy loop (while (1)). However, that burns power, and I am looking…

    • Answered
    • over 2 years ago
    • Processors
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  • how dose the PC run to startup.s when the mcu reset

    rookie enginner
    rookie enginner

    Hi,dear enginner:

        i want to know how the PC run to startup.s when mcu reset?

       The Definitive Guide to the ARM Cortex-M3 says address 0x00000000 is MSP‘,address 0x00000004 is ResetVector.

       But when I look at STM32F767, I find that 0x00000000 and…

    • Answered
    • over 2 years ago
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  • DWT

    Gabor M.
    Gabor M.

    Hello,

    I use DWT in Cortex-M4 to catch instructions that write or read memory contents and the problem is it doesn't stop immediately where I expect, it stops after 2-3 instruction later than where it should and the contents of registers are overwritten…

    • Answered
    • over 2 years ago
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  • Cortex-M register RAM and Flash periodical check?

    Half past nine
    Half past nine

    Hi ARM,

    How to check Cortex-M4 register,RAM and Flash periodically using software when the processor is running?

    Best regards,

    Frank

    • Answered
    • over 2 years ago
    • Processors
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  • Cortex-M0+ privileged/unprivileged extensions

    Jorge
    Jorge

    Hi all,

    According with ARMv6-M architecture reference manual, it supports two operation modes, handler mode and thread mode.

    - "execution in handler mode is always privileged."

    - "execution in thread mode can be privileged or unprivileged, depending…

    • Answered
    • over 2 years ago
    • Processors
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  • M0+ Stack Pointer (PSP/MSP) Clarification

    Sean Dunlevy
    Sean Dunlevy

    Background

     I'm working part-time on a Cortex M0+ based SoC converting a very processor-intensive section of C++ code (inner-loop executed 10s of 1000s of times a second & compiles to over 400 instructions using GNU O3) and after almost 3 months of work…

    • Answered
    • over 2 years ago
    • Processors
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  • I2S with ARM M0

    sushil chauhan
    sushil chauhan

    Can we connect I2S lines in the arm M0? If so any references??

    sushil

    • Answered
    • over 5 years ago
    • Processors
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  • Best ARM processor for a low power medical device

    Andrew Watters
    Andrew Watters

    I am working on an implantable medical device that requires a system on a chip.  I can probably manage 1.5 to 2.5 watts, and I'm going to need all of it for this application.  Which ARM processor should I use?  Thanks.

    • Answered
    • over 2 years ago
    • Processors
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  • How does Cortex-m4 core interact with other master devices?

    William Wong
    William Wong

    How does Cortex-m4 interacts with other master devices such as DMA while m4 core does not have Hbusreq and Hgrant ports? m4 core does not have interfaces to arbiter.

    • Answered
    • over 2 years ago
    • Processors
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  • How to use GPIO interface IPs of ARM Cortex M0+

    Sabarish
    Sabarish

    Hello,

    We bought ARM CM0+ deliverables from ARM. I want to design an SoC which has to get data from an another system .The aim of the SoC is to process an array of 4096 samples received from the external world.For the data interfacing, we are using GPIO…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Count the number of trailing zeros without clz?

    Will
    Will

    I am trying to count the number of trailing zeros in floating points without using the clz command. what would be the easiest way to rewrite this code?


    ctz
            RSB      r1,r0,#0
            CMP…

    • Answered
    • over 4 years ago
    • Processors
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