• Beginers questions regarding ARM development.

    travjav92
    travjav92

      I am just starting out developing with ARM and am really enjoying learning about these processors. I have a few questions that have been on my mind as a newbie that I'm hoping some people can answer.

     From my understanding, the ARM cortex m0 series…

    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • RFFT CMSIS-DSP - Fluctuating index

    SweetPotato
    SweetPotato

    I am using the Cortex M4 with CMSIS 5.4.0 DSP library. I'm using the arm_rfft_f32() function and the max_arm_f32() function to compute the maximum frequency bin of injected pure sine wave with an external CODEC. SSI0 and uDMA are being used to take in…

    • Answered
    • over 1 year ago
    • Processors
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  • Understanding XDMAC on Cortex-M7

    Paul Braman
    Paul Braman

    I've inherited some XDMAC code and no one that wrote this code really seems to be able to explain anomalies that I am seeing. So, I'm trying to understand just the basics in an attempt to make sure it was written correctly in the first place. Here we…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • setting breakpoint from code

    franto
    franto

    Hi, my app (cortex m3) needs to set up a breakpoint directly from code, in order to jump to an interrupt when an instruction from a certain address is fetched. This WITHOUT using a debugger.

    Any hint or tutorial? I think the only possible way is the patch…

    • Answered
    • over 1 year ago
    • Processors
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  • How to get started with ARM Cortex-M, RTOS, Linux?

    Hossein
    Hossein

    Hello everybody,

    As the senior expert I have worked with ATMega2560 so much, but I have to choose the ARM micro-controllers for my new projects.

    I have also read a lot about ARM7TDMI,focusing on how to write SWs with Keil...but I haven't had any practical…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M4 L1 data cache policy

    nothing
    nothing

    I have some confusions about the difference between write back + write allocate and write back + write no allocate on Cortex CM4.

    As my original understanding:

    • For write back with write allocate:
      • If write-address isn't cache hinted yet, cache line…
    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • IAR Compilation error

    myself_subhash
    myself_subhash

    Hi 

    I am compiling below assembly language code for ARM Cortex M4 using IAR Workbench and getting error, could some one help me on this. calling BadWebConfig_Txt from C code.

    #define code_ADDRESS(a) ((a)>>24 & 0ffH,(a)>>16 & 0ffH,(a)>>8 & 0ffH,(a) & 0ffH…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Buffer Depth of UART in Arm cortex M7 processor

    Jeevan
    Jeevan

    Can any one tell me what is the Buffer Depth of UART in Arm cortex M7 processor.

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • RNG (Random) on Cortex-M4

    Amir
    Amir

    Many implementations on Cortex requires true random number generation.

    It is very common to use seed based on the tick counter and then rand() function which is "just" a constant fixed known function.

    However, if after each reset, application…

    • Answered
    • over 3 years ago
    • Processors
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  • CMSIS FFT

    jay shah
    jay shah

    Hi All, My Question is related to CMSIS DSP Library. i'm working on ADuCM3029 EZ-KIT. I'm using IAR v7.8.1 to build the project. In my application i have an ADC interfaced with the controller, from which i acquire 60 samples and stores it into the buffer…

    • over 3 years ago
    • Processors
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  • Suitable ARM processor for Traffic Lights Controller

    Nikl@s
    Nikl@s

    Dear Mrs. /Mr.

    We are a company that manufactures traffic light systems. Our RnD department is in the designing process of a traffic light controller (TLC). The basic operational bloc diagram of the system is shown on the following figure:

    As you can…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Optimized RGB to YCbCr conversion on Cortex-M7

    Ilyes Gouta
    Ilyes Gouta

    Hi,

    Does ARM make available optimized routines for RGB/YCbCr conversions (e.g. RGB16/RGB888 to YCbCr 4:2:0 and 4:2:2) on Cortex-M7 (e.g. using SIMD instructions and intrinsics)?

    (and in general, is there such an optimized library for DSP and image processing…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex-M7 minimum schematic ?

    dgubber
    dgubber

    I'm looking to start a new design based on the ARM Cortex-M7 and have been reading thousands of pages of documentation ( not done yet of course ). I am able to design my own schematics and PCBs so I'm trying to first determine the very bare minimum to…

    • Answered
    • over 3 years ago
    • Processors
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  • CM4: Is DAP immune to MPU protections?

    SysTom
    SysTom

    Can the DAP cause exceptions by performing illegal instruction in spaces protected by MPU or is it immune?

    Trying my hand at setting up MPU but I cannot get it to fire - thought it might not be possible with DAP.

    Thanks, Tom

    • Answered
    • over 3 years ago
    • Processors
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  • Arm Instruction Set (Thumb-2)

    AbdAllah Talaat
    AbdAllah Talaat

    Hi , I am New to this Community

    I am Studying now Cortex-M3 .. I am reading Joseph Yiu book...

    I am Confused in the part of the instruction set , and I couldn't get the following:

    as i understand that some of the original ARM 32-bit instructions are…

    • Answered
    • over 3 years ago
    • Processors
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  • Problem with SWO when debugger not connected

    ciaranmac
    ciaranmac

    Hi,

    I have configured my M4 based CC3200 from TI to output printf via ITM (all uarts used). Works great as long as the debugger is connected. But when I boot up with no debugger it streams out unrecognisable packets. The normal packets are one header…

    • over 3 years ago
    • Processors
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  • What does system memory work actually?

    ele
    ele

    Hi.

    Currently. I'm trying to understand about system memory in cortex m3 address map.
    most examples are said "there are 2 area such as 0x08000000 Flash memory area and
    0x1FFFF000 System memory area.

    and I understood that Flash memory area is saving…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Help Choosing a processor

    strawberryfieldsforever
    strawberryfieldsforever

    I have been given the task of selecting a suitable processor for a project in which we will have a dedicated processor.

    The project will involve configuring HW and inverting matrices in C.  We will use the Cholesky algorithm in double precision.  We don…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • What is the relationship between UART and printf within retarget?

    ele
    ele

    HI.

    I'm trying to understand the relationship between UART and printf within retarget.

    as I understand, retarget supports to implement low level function fputc, if I want to use printf().

    if I am right, I can't still understand the relationship between…

    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • [CM4] Best general way to handle a hardfault/lockup

    sfoster
    sfoster

    Over the past few months I've been doing a lot of work on a Kinetis K24 processor, which is a Cortex-M4, running the MQXLITE RTOS. It also has a couple other SDKs built in and a surprising level of complexity for a CM4 application. What all that leads…

    • Answered
    • over 3 years ago
    • Processors
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  • CM4: Can processor halt itself by writing DHCSR

    SysTom
    SysTom

    Hello,

    As part of my diagnostic regime I wanted the diag to halt when completed.  It doesn't seem like it can.  It seems to keep running when I 

      CoreDebug->DHCSR = (0xA05FUL << CoreDebug_DHCSR_DBGKEY_Pos) |
                         CoreDebug_DHCSR_C_HALT_Msk…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Software interrupt generation on Cortex M33.

    sdiwakar
    sdiwakar

    Hi,

    On Cortex M33 , i am trying to check software interrupt functionality. Below is the CMSIS APIs i used.  Note that the CPU is in secure world and secure VTOR is being configured.

    Also, ITNS config for this line is set to secure.

    NVIC_SetPriorityGrouping…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M4 Conditional Branch - Pipeline

    fede_cip
    fede_cip

    Hello all!

    So I'm working on a development with a Cortex M4 and there is something i don't understand, I was hoping someone could help clarify this:

    This is the code I' using

    (Assume R3 content is 1, R6 R8 the address needed to set PIN1, and…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Where could I find a good start for studying Memory Types and Attributes as well as Monitors and semaphores ?

    AbdAllah Talaat
    AbdAllah Talaat

    Hi I was studying the memory system ... and I found three related concepts/topics but I couldn't grasphow these concepts are related to each other and to the AMBA Protocol ... these concepts are : - memory Type - memory Attributes - Monitors and semaphores…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • CM4: Write buffer with enabled MPU

    Matic
    Matic

    Hello,

    I have a question regarding Memory protection unit on Cortex M4 (STM32F3 MCU). This is pretty simple single core MCU without caches. I implemented MPU based on instructions in Definitive guide to the ARM Cortex-M4. It is stated there that the bufferable…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
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