• ARM Cortex M3 STM32F207 processor hangs during the initializing if the code-size is more then 64k

    Stefan Tesche
    Stefan Tesche

    Hallo,

    I'm using a ARM Cortex M3 STM32F207 processor and if the code of  my project becomes a value of more than 64k, the processor hangs before the PC reach the __main().

    The code starts at 0x08020000 (sector 5) and hangs at a Breakpoint or any…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Indication to begin a program

    amrani joutei
    amrani joutei

    I need some indications to begin writing a program.

    Write a compare routine to compare 64-bits values , using only two instructions.

    Thanks for your indications !

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • [CM3]assembly language trouble

    stupidMokey
    stupidMokey

    CORE: STM32F103ZET6

    Hi,Pros.

         Here Monkey comes agian

    I have met a problem with my code,see below:

    /* --------- code here --------- */
         .section .data
    _sp_usart:
         .word     _stack_usart
    _stack_usart:
         .space     0x100…
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • [Cortex-M0] Thumb mode & code size

    wshen
    wshen

    Hi,

    I'm somewhat confused with the Thumb mode code size.  My understanding is compiling with ARM mode will generate 32-bit instructions and compiling with Thumb mode will generate 16-bit instructions.  When I compile my Cortex-M0+ project (which should…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • ARMv8 exception vector significance of EL0_SP

    armdev
    armdev

    Hi,   I am new to ARMv8 architecture and while reading the v8 exception vectors I am not able to understand significance of adding SP_EL0 level vectors while SP_ELx vector set exists. What I am trying to find a use case where this is useful. I understand…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • system requirements

    SGR
    SGR

    what are the minimum hardware requirements to setup wifi on arm-7 processors.

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • ARM Cortex-M0 Details

    Indira
    Indira

    I am doing my PhD in Computer engineering and have developed a processor which is similar to ARM Cortex M0. I have got the obfuscated code and tried to make the comparisons.  I was wondering if anyone could give me the details on the area, speed and power…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Compute the division via shift instruction

    gapry
    gapry

    I write the code as following to evaluate the expression n = n / 2

    asrs r0, r0, #1

    But, I found the GCC will translate the expression n = n / 2 into the following instruction

    lsrs r1, r0, #31                                                                             

    adds r0, r1, r0

    asrs r0, r0, #1

    Why does it need to add the…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How long are the Cortex-M7 pipeline stages?

    Yasuhiko Koumoto
    Yasuhiko Koumoto

    Hello experts,

    recently ARM updated the Cortex-M7 information.

    I think the biggest topic would be that the pipeline details were opened.

    The new information says that the integer pipeline is 4 stage and the floating point pipeline is 5 stage.

    However, the…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Break Points and Watch Points

    harshan
    harshan

    Greetings,

                   Sir,i am working on SWD, after  Research on Break Point & Watch Point i found One Thing That There are Some Comparators will Do These Things but I am not Very Sure That How These are Work …

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Get current active interrupt priority

    Jonathan Weber
    Jonathan Weber

    Hi everybody,

    We are working on a simple priority RTC (run to completion) framework for the Cortex M3/M4. Thanks to the NVIC/BASEPRI, we got most of this functionality for free but we want to extend it to user tasks.

    In our implementation we need to determine…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Continue the Target using Serial Wire Debug Protocol

    harshan
    harshan

    Greetings,
                   sir, i am working on serial wire debug protocol and till now i succeeded in halt,write,erase,and reset the target. now i am trying to implement breakpoints and watch points on my custom debugger. for break point i read "the definitive…

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How many times same interrupt can be in pending state at a time? (In ARM CM-3)

    sandeep tayal
    sandeep tayal

    Could not find the answer to How many times same interrupt can be in pending state at a time? (In ARM CM-3) e.g. :

    We are processing one interrupt INT_RX, at the same time 3 more packets received. so I expect 3 times more this interrupt to appear sequentially…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to acknowledge/clear active interrupt in Cortex-M4

    Deepak Jharodia
    Deepak Jharodia

    Hi all,

    I'm testing interrupt on a Cortex-M4 based platform. So far I have managed to get my interrupt handler called. It clears the interrupt source coming from the peripheral. But before the pin to NVIC is de-asserted, the handler is called again. At…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex-M7 "zero overhead loop"

    Ari Mendes
    Ari Mendes

    Hi.

    In the page 22 of the document below informs that the cortex-m7 has "zero overhead loops" capability. I would like to know how it is done? Is there a special instruction for it?

    http://community.arm.com/servlet/JiveServlet/downloadBody/9595…

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Return address from FIQ_Handler. Do we come back to the next instruction?

    Harshdeep
    Harshdeep

    Is it

    MOVS pc, r14

    or

    SUBS pc, r14, #4

    This is written in the ARMDEN0013D. but in the table it says next instruction whereas the SUBS pc, r14, #4 means the instruction which was interrupted.

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Which is best ARM starter board for 32 Bit 3D printer?

    Lindsey Scott Lewis
    Lindsey Scott Lewis

    Hello I was curious about which ARM launch/starter board would be best used to create an electronics controller for a 32 bit 3D FDM printer?  I was thinking that I've seen one project for the TI TM4C123G launchpad that might work.  But are there better…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • CPU Reset during a Debug session

    Kashif
    Kashif

    Hi All,

    I am trying to reset the CPU in the middle of a debugging session. I am using Application Interrupt and Reset control register by setting the SysResetReq bit in the SCB block. (this preserves the current debugging session also).

    However, as I am…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • [CM3]which clock sources can be closed?

    stupidMokey
    stupidMokey

    Hi bro,I am wondering which clock sources can be closed by software within stm32?thanks for helps.

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Fastest way to transpose array in cortex-m4?

    Josh Jordan
    Josh Jordan

    I've been seeing situations where I want to take a 32bit array of 32 elements and copy it so that all the bit 0s are copied into element 0, bit 1s copied into element 1, etc for all 32 elements.  This is always the processing bottleneck for applications…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to get Cortex m3 soft core

    Vivek Jayakrishnan
    Vivek Jayakrishnan

    Hi,

    I needed to know where i could get arm cortex m3 soft core. Its for my masters thesis for which i'll be also using Keil uvision 5.

    Thanks in advance

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex M4 Unaligned access with STR single word access

    Saqib Ahmed
    Saqib Ahmed

    Hi there,

    I am getting a hard fault for accessing an unaligned memory address with STR single word access on a cortex M4 processor (Infineon XMC4500 F100k1024). Cortex M4 manual says that:

    Unaligned support is only available for load/store singles (LDR…
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Problem: WFI instruction slowing down SYStick interrupt

    Saqib Ahmed
    Saqib Ahmed

    I've configured my Infineon relax kit for max frequency(120 MHz). I've set my SYSTick for a periodic interrupt of 10 ms. For power saving, I use a WFI assembler instruction whenever my processor is idle. WFI (wait for interrupt) should put the processor…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • What is the advantage of floating point of CM7 versus CM4

    Rastislav
    Rastislav

    Hi all,

    I did some of the investigation based on comparison of FPU based algorithms on CM4 and CM7 cores. All the code/data were placed into the single cycle memory with full utilization of modified / true Harvard architecture, it means:

    - on CM4 - code…

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • 1-cycle multiply, 64-bit result,  reciprocal?

    Sean Dunlevy
    Sean Dunlevy

    Can someone tell me how many extra gates the 1-cycle multiply uses? If there was a 64-bit result, how many more gates would be used? Can these gates also be used to find the reciprocal of a number so instead of divides, the coder multiplies the reciprocal…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • View related content throughout Processors
  • More
  • Cancel
<>