• Cortex M7 : Exception return query

    Ritesh Joshi
    Ritesh Joshi

    Hi I am working on Cortex M7. I am generating some interrupts and according to it my ISR is being called which I have already installed. After the execution of the ISR the PC is not returning to the instruction at the time of the interrupt, due to which…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • My application seems to be dropping interrupts; does returning from an interrupt clear its pending flag?

    Rohit Grover
    Rohit Grover

    I'm working with a Cortex M4 (Freescale's Freedom-K64F dev-board). I'm trying to write a long sequence of data to flash. The state machine for this sequence operates in the interrupt handler. This means that in the handler for the processor's flash-controller…

    • over 4 years ago
    • Processors
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  • Verilog bus functional models for AHB master simulation

    Gord Wait
    Gord Wait

    I see in the documentation site that ARM offers up some bus functional models to simulate both a 32 and a 64 bit AHB bus master in Verilog RTL.

    Where do I find these models, and what is the cost?

    I am working to verify a customer's AHB peripheral, and…

    • Answered
    • over 4 years ago
    • Processors
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  • Will data be stored to cache first when I send a large amount of data continually(exceed the size of cache)?

    amanda_s
    amanda_s

    Dear friend

       Cortex-M7 has cache. After enable data cache, will data be stored to cache first when I send a large amount of data continually?

       The size of data exceed the space of cache.

       Thanks!

    Amanda

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Synchronization primitives, do I need CLREX?

    Jan
    Jan

    Hi all,

    I'm trying to understand the LDREX/STREX commands in an ARM Cortex M3 MCU to implement atomic access to various variables (the goal is to implement semaphores/mutexes or increment/decrement shared variables).

    There are several ressources available…

    • Answered
    • over 4 years ago
    • Processors
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  • implementing a hardware on nexys 4 ( corterx-m0)

    mariam
    mariam

    hi, as i posted before I'm trying to integrate an adder to my architecture however no body replied

    so please if anyone succeeded in implementing a hardware design on his FPGA, and of course when i say a hardware design it doesn't include the predefined…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • about tail chaning of Cortex-M0

    下田敏郎
    下田敏郎

    Hello.

    I'm studying about the tail chaining of Cortex-M0.

    Is it same as Cortex-M3 or M4?

    Best regards.

    • Answered
    • over 4 years ago
    • Processors
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  • DSP instruction for x*x + y*y. Does it exist?

    Matic
    Matic

    Hello all!

    I am new to ARM community and this is my first question here. I work on embedded systems where we use Cortex-M4 based MCUs (concretely STM32F3 series). I would like to ask, if there is a DSP instruction which would calculate x*x + y*y.

    x and…

    • Answered
    • over 4 years ago
    • Processors
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  • Cortex-M7 Load/store timing execution ?

    M.Azrul
    M.Azrul

    I'm not a native English speaker. So, sorry for the broken English. I'm intend to develop a system where the microcontroller will interface with a 8 bit parallel port IC. The bytes will be loaded into the microcontroller at the specific timing. As documented…

    • over 4 years ago
    • Processors
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  • How to get absolute value of a 32-bit signed integer as fast as possible?

    Matic
    Matic

    Hi.

    I wonder how to calculate absolute value of a 32-bit signed integer in C as fast as possible. I saw that there is a FPU instruction VABS.F32, which do that in one cycle (above the floats). I thought, if it is possible to use it also with integers …

    • Answered
    • over 4 years ago
    • Processors
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  • Bit-banding in SRAM region (Cortex-M4)

    Matic
    Matic

    Hi.

    I would like to use bit-banding feature in SRAM, but don't know exactly how to implement it with C. I already use bit-banding in peripheral region with this kind of macro:

    #define BITBAND_PERI_REF        0x40000000…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Read/Write from register

    emna
    emna

    hi

    I'm using the soft-core Cortex-M0,keil uvision 5,vivado 14.4

    I am trying to implement a filter on my Cortex m-0 based FPGA

    the main idea of this project is to create an accelerator from my C code to reduce the execution time ..and since my accelerator…

    • Answered
    • over 4 years ago
    • Processors
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  • ARM CM4 FPU execption

    Anuj
    Anuj

    I am looking for FPU exception generation code. If some one share, or suggest some document for the same.

    Regards

    Anuj

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • cmsis NVIC question.

    Setianian
    Setianian

    Hello, Everybody. I have several questions.

    1. Please See the NVIC_Type structure. I don't understand about why ISER,ICER,ISPR and ICPR use size of array 1( I think It can use just __IO uint32_t ISER; ), and what does RESERVEDs do???

    2. I would like…

    • Answered
    • over 4 years ago
    • Processors
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  • coming from AVR 8-bitter,starting ARM CORTEX-M programming

    Luca
    Luca

    Hi everyone, as I wrote in the title, I'm coming from AVR 8-bit MCUs programming and in the last year I learnt a lot about AVR 8-bit architecture,CPU,registers and so on.

    I've done a few projects coding primarily in C and something in Assembly (serial…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Enabling NEON Instructions on Pixhawk

    Nathan Szanto
    Nathan Szanto

    I am trying to get a quadcopter flying using the Pixhawk controller (Cortex M4 running NuttX RTOS) and I am using the Simulink Pixhawk PSP to implement a custom controller. Our controller uses neural networks, so neon instructions are needed (the build…

    • Answered
    • over 4 years ago
    • Processors
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  • I have an Arm 32-bit Cortex V3.10, Does anyone know the manufacturer/email?

    jeff
    jeff

    I need a configuration to get rid of the spacing between the numbers in a single barcode.

    • Answered
    • over 4 years ago
    • Processors
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  • Bootloader. VTOR, BOOTPROT FUSE, JUMP to app and other related questions

    Iván
    Iván

    Hello everyone!

    I am writing here because I am having some issues developing my own bootloader. I am currently working with an ATMEL SAM R21 which has an ARM CORTEX M0+ in it.

    Firstly I am going to summarize the more relevant points (or I think those are…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Is ARMv7-M3 thumb instructions compatible to ARMv7-A thumb?

    Kaiyuan
    Kaiyuan

    Hello guys,

    I am trying to verify some features of ARMv7-M3 in a software simulator platform for ARM. But this simulator only support ARMv7-A ISA.

    Is ARMv7-M3 instructions compatible to ARMv7-A, especially thumb instructions?

    Thank you very much.

    • Answered
    • over 4 years ago
    • Processors
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  • lpc2148  library  bundles and c programming tutorial

    Gokhu
    Gokhu

    Hi Friends.. I am Gokhu..New to ARM..i start my learning process..i need library function of iolpc2148.h and main.h and stdio.h, RTC.h,ADC.h and DAC.h uart.h these kind of library bundle and i need a material or online site to learn arm C programming…

    • Answered
    • over 4 years ago
    • Processors
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  • Cortex M7 irq enable/disable

    Valentin
    Valentin

    In the appnote "ARM Cortex-M Programming Guide to Memory Barrier Instructions" there is a section that describes the use of memory barriers in the Cortex-M processors on a case-by-case basis.

    Are those cases relevant for the Cortex M7 - especially…

    • Answered
    • over 4 years ago
    • Processors
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  • Use of SV Call & NMI Exceptions in ARM

    Arun
    Arun

    What is the use or application of SV Call and NMI Exception in ARM Cortex M0 .

    Is it someway related to RTOS?, if so , how?

    • Answered
    • over 4 years ago
    • Processors
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  • Interruptible-restartable instructions and Others

    Kilian Timmler
    Kilian Timmler

    Hi,

    As I have found in:

    Cortex-M0+ Devices Generic User Guide: 2.1.3. Core registers

    There is information about instruction behaviour during interrupts:

    "Interruptible-restartable instructions

    The interruptible-restartable instructions are LDM, STM,…

    • over 4 years ago
    • Processors
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  • Race condition between wake up event and WFI on Cortex-M3/M4

    neo
    neo

    When I read below thread in arm forum, I still not clear which one is the safety way.

    Cortex-M4: guaranteed wakeup from WFI?

    There're two solutions mentioned above, using WFE instead of WFI, and swap __WFI() and __enable_irq().

    I can understand WFE…

    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • How to prepare ADC data for Q31_t CMSIS DSP functions?

    Andrea Bettati
    Andrea Bettati

    Hi to you all,
    I've another post on the forum (here's the link Process ADC data, moved by DMA, using CMSIS DSP: what's the right way? ), but since I think I made some small steps forward I felt I could be a little more specific. I hope this…

    • Answered
    • over 4 years ago
    • Processors
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