• stmdb instruction *appears* not to work correctly - Cortex M4 / SAM4L

    HarryAtElpro
    HarryAtElpro

    I'm struggling to track down a problem here. It appears to be that the stmdb instruction isn't pushing all of the requested registers, and when the corresponding ldmia.w instruction executes, it pops a PC value that sends the processor executing code…

    • 2 days ago
    • Processors
    • Cortex-M / M-Profile forum
  • Compiling libgcc not optimized

    EnricoTabanelli
    EnricoTabanelli

    Good moorning,

    I am trying to compile libgcc for arm-none-eabi target from scratch, since I need to compare Floating Point SW emulation on an ARM Cortex-M4 and Risc-V based processors. The problem is that by default GCC includes the optimized version…

    • 10 days ago
    • Processors
    • Cortex-M / M-Profile forum
  • FPB BreakPoint(without Debugger)

    shincm
    shincm

    Hello,
    My App (cortex m4) needs to set up a breakpoint directly from code, in order to jump to an interrupt when an instruction from a certain address is fetched.
    This without using a debugger.
    I searched in the forum and tried the method.

    1. DebugMon…

    • Answered
    • 6 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Speculative data fetching on ARMv7-M

    MikeRobo
    MikeRobo

    I am working with an ARMv7-M with a cache and trying to workout how the Speculative data fetching works or at least understand it.

    The only documentation I can find for it is a small section in ARM®v7-M Architecture Reference Manual.

    Any resources to…

    • 6 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • Changing prio of running IRQ triggers hardfault

    Vinci
    Vinci

    Hello

    I've a question regarding the NVIC on Cortex M4 devices. Up until today I was under the impression that changing the priorities of a running interrupt isn't an issue in the ARMv7-M architecture, but the following pseudo-code snippet keeps triggering…

    • 9 months ago
    • Processors
    • Cortex-M / M-Profile forum
  • ARMv7M RefMan: What is "Rn" for "MVN"?

    Niklas
    Niklas

    Hello,

    in the ARMv7M Architecture Reference Manual version E.d in the documentation for "MVN (immediate)" on page A7-303 it says:

    "<const>  Specifies the immediate value to be added to the value obtained from <Rn>"

    What is…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-M / M-Profile forum
  • Could you explain BCC command to me?

    Robert
    Robert

    Hi,

    I find C code not executing in the desired way. Then I step in assembly code of Tiva-C M4F core. Below is the disassembly code:

    $C$L5:   nop

    0000033a:   280A     CMP             R0, #10…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Synchronization primitives, do I need CLREX?

    Jan
    Jan

    Hi all,

    I'm trying to understand the LDREX/STREX commands in an ARM Cortex M3 MCU to implement atomic access to various variables (the goal is to implement semaphores/mutexes or increment/decrement shared variables).

    There are several ressources available…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • v7M debug architecture questions

    cray
    cray

    Dear sirs,

    Regarding v7m debug architecture, I have some questions after reading the v7m architecture document.

    Q1: There is no mechanism to send instruction to the core for execution in debug state, is that true?

    I guess the architecture uses  debug return…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Hard Fault in cortex m4

    hemant
    hemant

    Hello All,

    Good Morning!

    I am working on Cortex m4.

    I have read following about hard fault ,

    "Bus Fault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and register stacking (save/restore) on interrupt (entry/exit…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Problems with interrupting LDM/STM Cortex M4?

    Paul Giangrossi
    Paul Giangrossi

    I am seeing stack corruption running a Cortex M4 that seems to be related to interrupting multicycle instructions.

    The interrupt occurs during a STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr}

    The ICI bits at the time of the interrupt equal 7. This means that…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Current priority level of processor

    Gopal Amlekar
    Gopal Amlekar

    Hi,

    I have been reading about the exception mechanism of Cortex-M (M4 to be precise). The exception request is accepted by the processor if the current priority level of the processor is less than the incoming exception (this is one of the conditions to…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • NXP LPC2378 (ARM7 core) communication via SPI protocol

    Raza Kamal
    Raza Kamal

    I want to communicate NXP LPC2378 (ARM7 core) to some other devices via SPI (Serial Peripheral Interface) protocol.

    So how to write a C code to communicate a particular device as a Slave with Master (ARM7 controller)?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Information on the Cortex-M7

    Jens Bauer
    Jens Bauer

    I believe that many of us are interested in the ARM Cortex-M7.

    Recently, jyiu posted a status update, where I asked a couple of questions about the architecture.

    A few questions on the subject was also asked in the Interview and Question Time with Joseph…

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Indication to begin a program

    amrani joutei
    amrani joutei

    I need some indications to begin writing a program.

    Write a compare routine to compare 64-bits values , using only two instructions.

    Thanks for your indications !

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • ARMv8 exception vector significance of EL0_SP

    armdev
    armdev

    Hi,   I am new to ARMv8 architecture and while reading the v8 exception vectors I am not able to understand significance of adding SP_EL0 level vectors while SP_ELx vector set exists. What I am trying to find a use case where this is useful. I understand…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • system requirements

    SGR
    SGR

    what are the minimum hardware requirements to setup wifi on arm-7 processors.

    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Break Points and Watch Points

    harshan
    harshan

    Greetings,

                   Sir,i am working on SWD, after  Research on Break Point & Watch Point i found One Thing That There are Some Comparators will Do These Things but I am not Very Sure That How These are Work …

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • two’s complement

    thewal
    thewal

     How to load the two’s complement representation of -1 into Register 3 using one instruction?

    i am working on ARM7 and NXP processor.

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Endian in Cortex-M4

    HimanshuDoshi19
    HimanshuDoshi19

    Hello to all,

    I am working on ARM Cortex-M4. Since it has 32-bit address bus, therefore I assumed that each 32-bit instruction will be allocated a physical address location in the Flash. But while reading the disassembly of the code, I got to know that…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • mismatch between ARMv7-M ref manual and core_cm7.h

    jheissjr
    jheissjr

    The ARMv7-M reference manual notes there eight ITM trace enable registers called ITM_TER0 to ITM_TER7.  However, core_cm7.h only has one ITM_TER register.  Can you clarify?  Is it an error in core_cm7.h?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Cortex-M RTOS related exceptions and concepts

    Karolis
    Karolis

    Hello,

    Recently, I came back to digging into RTOS working principles at the lowest level on Cortex-M family processors. I understand the concept of SysTick (or other time base), SVC and PendSV as RTOS system exceptions. Though, one question is still itching…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • Is SVC pendable on cortex-m?

    loquat3
    loquat3

    Hey.

    I read ARMv7-M Arch manual.

    SHCSR register have SVCALLPENDED bit.

    So that, It seem SVC is pendable.

    But, 'Priority escalation' is written,

    When the group priority of a pending synchronous fault or supervisor call is lower than or equal to…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • DMB, DSB, ISB on Cortex M3,M4,M7 Single Core parts

    Trampas
    Trampas

    I have been reading through the ARM documentation on memory and instruction barriers. 

    I have read that the single core ARMv7-M parts do not reorder instructions, as such the DSB and ISB are not needed, is this correct? 

    I have also read the same about…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • When an exception is taken into account

    Karolis
    Karolis

    Hi

    Related to ARMv7-M architecture:

    I am searching through all infocenter documents but still cannot find anything and answer this question: "When an exception is taken into account?" I mean, are exceptions only serviced after the current instruction…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-M / M-Profile forum
  • View related content throughout Processors
  • More
  • Cancel
>