• Data abort, External abort.. How can i find cause????

    Yeo Reum Yun
    Yeo Reum Yun

    Hi, experts

    I'm developing Secure OS on A57/53 bit.LITTLE SoC. But as you know.. Cuz i'm really beginner..

    I beg your wisdom...

    Current situation is :

    • For making a TA. Bring the related data from REE and Mapping TEE side's NON-SECURE memory. (Data…
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory?

    Yeo Reum Yun
    Yeo Reum Yun

    Hi Experts,

    I'm reading white paper for ARMv7 and ARMv8.

    but when i reading cache part and memory re-ordering, i have silly questions.....

    Suppose there are below instructions..

     

    Core A:

         STR R0, [Msg]

         STR R1, [Something…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
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