Hi,

i'm currently trying to measure cycle counts for FIR-filtering with the NE10 library. I'm using a Raspberry Pi 2 with ARM Cortex-A7 running on Raspbian as a target.

I activated the Cortex-A7 performance counter register to read out the cycles…

Hello all,

I wrote end embedded assembly function for an ARM Cortex A9 (the specific device is Zynq, from Xilinx) as follow

float my_fun(float x)

{

                asm volatile ("vdup.f32 d0, r0                     \n\t");…

Dear,

I am an greenhand developer on cortex-a15.

now I need some specification as follows:

where I can get the instruction set of cortex-A15?

are there some documents about optimization technology on cortex-A15(image processing optimization)

Thanks a lot.

HI,why the VFP vector mode can not be used in cortex-a series processors?

Hi, can anyone suggest me how to know the instructions cycle timing of the arm_v8 instructions.does it take more cycles to transmit from neon to basic arm instructions in arm_v8.

please suggest me how to calculate instruction cycles in arm_v8

In NEON spec:

VCLS (Vector Count Leading Sign bits) counts the number of consecutive bits following the topmost bit, that are the same as the topmost bit, in each element in a vector, and places the results in a second vector.

VCLZ (Vector Count Leading…

=======================================

for matrix 4 by 4 multiplication, neon programming is slower than natural code with

auto-vectorization option. (Xilinx Zynq 702 EVM board - cortex a9 with gcc complier option

-mfloat-abi=softfp -mfpu=neon-fp16 -ftree…

I'm seeing Cortex-A7 cycle-timing table here :

http://hardwarebug.org/2014/05/15/cortex-a7-instruction-cycle-timings/

For example, 

VADD.F32 Dd, Dn, Dm takes 2 cycles

VADD.F32 Qd, Qn, Qm takes 4 cycles

same goes for VMUL..

Is this really the case…

The cortex-A7's pipeline support dual-issue, so I want to ask what's the dual-issue mean?

I find some answers say that dual-issue means that the cortex-A7 can issue two instructions per clock.

But in the cortex-A7's pipeline diagraph, it has integer…

Hi,

I have used some 32-bit microprocessor cores (non-ARM), which has a long word-length accumulator for some DSP operations, to avoid over-flow etc. After I check A8 core document, it is a surprise that I do not see any about this specification. It looks…

Hi,

      I am using beaglebone which has the processor TI Sitara AM335X. I want to make use of Neon coprcessor for my project, To enable neon, I have to follow these commands. But I can't access these registers ( especially FPEXC…

Hello,

I’m new to ARM architecture and was looking to get a better understanding of how it works. Most notably, the Cortex-A series and its DSP functionality.

When looking through the NEON SIMD page on ARM's webpage (NEON - ARM), it mentions that…

Hello,

I’m new to ARM architecture and was looking to get a better understanding of how it works. Most notably, the Cortex-A series and its DSP functionality.

When reading through ARM’s webpage, it often refers to “NEON-Advanced SIMD”, “NEON”, and…

Hi, experts

I'm developing Secure OS on A57/53 bit.LITTLE SoC. But as you know.. Cuz i'm really beginner..

I beg your wisdom...

Current situation is :

• For making a TA. Bring the related data from REE and Mapping TEE side's NON-SECURE memory. (Data…

Hi Experts,

I'm reading white paper for ARMv7 and ARMv8.

but when i reading cache part and memory re-ordering, i have silly questions.....

Suppose there are below instructions..

Core A:

     STR R0, [Msg]

     STR R1, [Something…

Hi Experts,

A8 is meant for single core and A9 is for multi-core based.

Consider in case of SoC is build with single core of A9 and A8 how we could compare both in terms of some metrics/parameters like power/speed ?

hi i am trying to understand ARM NEON instruction and encountered with vqrdmulh instruction.

i am particularly interested in saturation case in instruction i am not getting any case with saturation .

Can any one explain me with an example

for example:

vqrdmulh…