Hi,
This question is for MMU and d-cache. When I tried to enable MMU and d-cache for u-boot I ran into Synchronous Abort handler while writing to PCIe device registers which I mapped as uncached memory. The dump is shown below
"Synchronous Abort" handler…

Hi ,

I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core.

Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn't see any Drhit,Dwhit event count register gets updated…