From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions:
SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated
as Non-Cacheable:
• all pages marked as Write…
Hello,
I would like to know how to read the translation table info for A9 from embedded Linux.
In freeRTOS I have translation_table.S but I do not find anything similar for ARM architecure in linux kernel.
Should I just dump TTBR0/TTBR1 registers…
I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib).
On the shared SDRAM, I am planning to have dedicated memory regions for each core, and a shared…
Hello,
I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9).
In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches, MMU and Program Prediction.
What I need is to know…
Hi
I have written a bareboard code for i.MX6 (Cortex A9 Quad core). I am activating and using only one core. Once I enable the MMU, code throws random exceptions. Both L1 and L2 caches are disabled. The interesting part is that if I just map the memory…
Hi ,
I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core.
Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn't see any Drhit,Dwhit event count register gets updated…
