From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions:
SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated
as Non-Cacheable:
• all pages marked as Write…
Hello there,
I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core.
I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and cache
Steps :
1.Disable cache, branch predictors
2. Invalidate…
Hello,
I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9).
In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches, MMU and Program Prediction.
What I need is to know…
Hi ,
I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core.
Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn't see any Drhit,Dwhit event count register gets updated…
