Hi,

I have a question on ARM page table.

I am running a bare metal application on Cortex A72 and i have a failure with my application.

Upon debugging the failure, i found an address which is contributing the failure. our Bare metal application is responsible…

I'm porting our armv7a-short descriptor OS to LPAE and aarch64. In the short descriptor MMU, the "NS" bit can only be found in the first level of the MMU (I'll call it the SECTION level), meaning that only a single page cannot be tagged as NS, a whole…

Hello all,
I want to improve VM operation in AArch64 port of FreeBSD but I stuck on following problem.
The FreeBSD VM subsystem is capable to map various *kernel* objects by using superpage (higher order) mapping. But in lifecycle of these objects (because…

Hello everyone,

I'm trying to wrap my head around the MMU configuration for Cortex A53 armv8 architecture (AArch64). Specifically, I'm programming for Raspberry Pi 3 (Bare Metal).

I've successfully setup the page tables for two levels covering…

Hello everyone,

I'm experimenting a bit with MMU after understanding its core principles. Specifically I can successfully enable it with an identity mapping for TTBR0 (no TTBR1) on a Raspberry Pi 3 (Cortex A-53, ARMv8 AArch64).

The next step I wanted…