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Hello,

I am using a quad-core Cortex-A7 (on Raspberry PI 2). I run a Linux on Core 0,1,2 and a baremetal application on Core 3. My goal is to protect the baremetal application from the rest (i.e., the linux side). Initially I thought that I can do this…

Hi,

I am just trying to learn the linux kernel booting process for arm32 Cortex A9 multi core SOC. I had understood the concept of booting in linux, but I am confused about the section where secondary cores enabling from primary core. Can somebody briefly…

I am trying to run two Cortex-A7s in AMP configuration with Linux running on one core (SMP disabled) and baremetal/RTOS running on other core. I am having difficulty in setting up SGIs (IPIs) between the two cores. I am at a point where both of the cores…

Greetings,

In my journey to learn ARM assembly using Android (Linux) systems, I'm currently playing with Thumb mode.

I'm currently testing if it is possible to write (ELF) library procedures entirely in Thumb. ATM, such tests only led me to Segmentation…

hey,

How to modify the value of AWCACHE [3:0] and ARCACHE[3:0] in AXI?

in baremental driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x00,

but in linux driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x01,

can anybody tell me…

  hello, I want to use DMA 330 asm code, but i can't compile it. can anyone tell how to use the PLL330 DMA assembly code? or tell me how to use the DMA for Cortex-A9

Hi,

I am experiencing A complete arm core hang when both of the cores are employed in SMP mode and using DMA.

I was tested with Linux kernels 3.10, 4.1 and 4.6 in SMP mode.

SOC used is Altera Cyclone V SOC-FPGA with dual Cortex A9.

The DMA transfer goes from…

Hi,

I'm using a Juno r1 board and I'm trying to get processor's related CPU ID without using any header file like function sched_getcpu from sched.h.

The reason is I want to get the CPU number for TrustZone application and there is no way to…

Respected Experts,

                              I would like to know that is it possible to get the advantage of Hardware Asssited Virtualization to develop a Type 2 Hypervisor which runs on …

All,

When I am using the cycle counter in AArch64, I am not getting cycles properly. I have enabled read of pmccntr_el0 in user space using a small kernel module. I have sample code like:

asm volatile("isb;mrs %0, pmccntr_el0" : "=r"(prev));

    sleep…

Hi Forum,

Why Cortex-R series is real time oriented than other ISA(ARM/others) ?

Is there a list of all the points and comparison with ARM Cortex-A ?

Why we can not make Cortex-A to suite for real time, which brings to think of Cortex-R ?

I am trying to understand…

Hi All,

I am using ARM v8-A Foundation Platform to debug my code. According to user guide, the base address of UART0 in system is 0x1c090000, so I use the following code to try to print a char via UART0:

*(volatile unsigned char *)(0x1c09000 + offset_of_tx_fifo…

Hello,

i want to use the arm cortex a9 to share memory between both cores. are there any examples online?

Thanks,

Mike

hi, guys:

Currently, i want to execute a Cotex-A9 binary compiled by ARMCC on Juno board(OS is linux).

But when i ran it, it reported that "XX: No such file or directory".

My questions are:

(1) Did somebody meet this problem before ?

      and could…

For ARMv7 -A/R systems, the MMU uses an ASID to distinguish between memory pages which have the same virtual address, but which are used by an individual task ( I.e. A task which uses non-Global memory). The ASID is an eight-bit value, from 0-255, assigned…

ARM friends,

I have done some research on software radio based on ZedBoard and AD-FMCOMMS1-EBZ.

ZedBoard is a development board which uses Xilinx Soc FPGA.

Xilinx Soc FPGA includes ARM Cortex A9 dual-core and Xilinx FPGA.

ZedBoard runs Ubuntu Linux operating…

Hi, all

When I was porting Minix 3 OS to Zedboard (Zynq 7000 All Programmable SoC) the system always hanged

at refresh_tlb. What's strange is that refresh_tlb had been performed at KERNEL booting up, but when a user

space process VM (for Virtual Memory…

Hi,

I have a beaglebone black and running a very basic app using starterware. As soon as the app starts executing i copy the CPSR values in memory. The value of CPSR is super surprising

6000019f

which means it is in SYS mode and IRQ, ABORT disabled and FIQ…

Hi, we are using arm cortex-a9 booting from spansion s25fl256. We are confused why the spi driver forces to limits flash size to 0x1000000 (16M). It's normal when first bring up and into linux. However, we find the uboot is broken or overrided and can…

Hi,

I am trying to understand if Guest OS data abort happens due to accessing some memory (e.g GIC distributor space) then is there any way I can route it to EL2 mode ?

I looked into HCR_EL2 register bits and tried setting AMO bit but it doesn't help. I…

Hi Experts,

What is the practical use of self hosted debug provision in the ARM V8 architecture ?

What are all the exceptions arrived and how it is handled ?

Regards,

techguyz

Hi Experts,

Does the EL3 and EL2 usage is the purely implementation specific or even though EL3 is implemented is it possible to disable EL3 and EL2 in software ?

Regards,

Techguyz