Hello,
I am working with a port of FreeRTOS on Arm64 soc , which is running at EL1, my goal is to perform a function call that will execute in EL0,
I have come to understand that the only way for the EL switch is to set the correct M bits of the spsr_el1…
Hi ARM folks, hoping someone can show me where I'm going wrong programming the MMU. The ESR_EL1 reports that it is a Permission fault, level 2. Here's what I'm trying to accomplish:
4GiB space, 4kiB granule flat identity mapped, divided like…
Hi all i trying do transition from EL3 to EL2 exception ,but after ERET of EL3 mode it change the mode to EL2 , but as soon as when it will execute first instruction of EL2 , then It goes to Exception ...
This is happen for every secure to non secure transition…
I have successfully moved from EL3 to EL2. After doing some initialization I am trying to move from EL2 into EL1 with a very simple guest image. My process looks like:
hi, expert
i study ArmV8 architecture.
On taking an exception to a higher Exception level, the Execution state either:
• Remains unchanged.
• Changes from AArch32 state to AArch64 state.
i konw that…
Dear sirs,
I'm reading arm v8a specification. I found that when arm is in aarch32 state, only a few exceptions can switch to aarch64 depending on the configuration in the registers. the exceptions are as follows.
abort, physical async abort, physical…
Hello, everyone
I'm new to this community.
I'd like to ask many questions and want to help someone.
Now I have some difficulties in understanding aarch64's watchpoint exception handling scheme.
I found I can decide which exception level whachpoint…
Hi,
I am experimenting execution level switching on A53. I go from EL3->El2, then call SMC instruction to return to EL3. As soon as SMC instruction is executed, the processor enters EL3 mode and an exception is generated.
I have written an exception…
Hi Experts,
ARMv8 MMU TTBRn_ELx registers are banked by exception level.
In "DDI0487A_b_armv8_arm.pdf" page 1640, the controlling register of secure EL1&0 stage1 is TTBR0_EL1
and Non-secure…
Hi, I'm reading SCTLR bit fields and have 3 questions.
1. In these bit fields (AFE, TRE, UWXN, WXN), there are comments like 'The AFE bit is permitted to be cached in a TLB.'
I can't figure out what the meaning of 'permitted to be cached in…
Hi,
I am trying to understand if Guest OS data abort happens due to accessing some memory (e.g GIC distributor space) then is there any way I can route it to EL2 mode ?
I looked into HCR_EL2 register bits and tried setting AMO bit but it doesn't help. I…
Hi Experts,
What is the practical usage of the ARM v8 virtual interrupts ?
How it helps in the performance of functionality ?
Hi,
I am facing issues with EL1 Guest OS. I have enabled EL2 stage 2 page tables and set up all the virtualization registers {HCR_EL2, VTCR_EL2 and VTTBR_EL2 etc.}
I am mapping my Guest OS memory to stage 2 tables but as I try to do "eret" from EL2…
Hi Experts,
What is the use case of the system error interrupts in ARM V8 and when it will be invoked ? Does it common to all the guest OS running in EL1 ?
Is it the physical input pin change like IRQs or instruction execution like WFE ?
Regards,
Techguy…
Hi Experts,
Does the EL3 and EL2 usage is the purely implementation specific or even though EL3 is implemented is it possible to disable EL3 and EL2 in software ?
Regards,
Techguyz
Hi Experts,
What is the reason behind allowing EL2 only in non-secured state in ARMv8 ?
Regards,
Techguyz
Dear Experts,
I would like to disable the data prefetching engines of the L1 and L2 caches on a MediaTek-X20 board which includes a quad Cortex-A53 cluster and runs Android.
I have tried to include in the Linux kernel code (at kernel/init/main.c) a call…
Hi,
In a GICv3 based system, is it possible to have the following configuration:
While running NS-EL1/EL0:
-NS Group1 interrupts triggered as IRQ to NS-EL1
-Secure Grp1 interrupts routed as FIQ to EL3
-Secure Grp0 interrupts routed as FIQ to EL3
This…
ARM V7 document states: "In ARMv7-A short descriptors only be used at EL0 and EL1 stage 1 translations. They cannot, therefore, be used by hypervisors or Secure monitor code."
Why stage2/hypervisors/secure monitor cannot use short descriptors…
Hi Expert,
I am working on a simple kernel and test it on Qemu which supports RasPi3. During the boot level. Ras Pi goes to EL3 level, and I set spsr_el3 to 1 and elr_el3 to kernel_main and then use eret to enter EL1 mode. My problem is I create a kernel…
Hi, arm experts,
We want to use ARCH32 mode in secure EL1, I see some descriptions in ARMv8 Arch Reference Manual about Secure EL1 ARCH32 mode as follows:
One is the VBAR(secure), it is mapped to VBAR_EL3, the other is SCTLR (secure), it is mapped to …
