• How should I do if I want to enable only one single CPU on a Cortex A9 MPCore(2 CPUs)

    onion
    onion

    Hi, all

    When I was porting Minix 3 OS to Zedboard (Zynq 7000 All Programmable SoC) the system always hanged

    at refresh_tlb. What's strange is that refresh_tlb had been performed at KERNEL booting up, but when a user

    space process VM (for Virtual Memory…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How can we boot linux kernel in ARM FVP w/ TrustZone?

    Yoshiharu Imamoto
    Yoshiharu Imamoto

    Hello, everyone.

    Let me post a question regarding booting Linux on ARM FVP (with Cortex-A9 MPCore).

    I'm setting up an experiment which uses TrustZone on ARM FVP. I'm not sure which

    kernel to run in the secure world, but am sure to run Linux in Normal…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to use the performance monitor of Cortex-A9?

    Yasuhiko Koumoto
    Yasuhiko Koumoto

    Hello experts,
    I feel I am an amateur.
    I tried to work the performance monitor of Cortex-A9 but it did not work.
    The followings are my codes.
    Please tell me what was wrong.

            mov     r3, #0
            mcr     15, 0, r3, cr9, cr12, {0} // PMCR PMU disable…
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex A9 boot from spi-flash 32M

    Daniel
    Daniel

    Hi, we are using arm cortex-a9 booting from spansion s25fl256. We are confused why the spi driver forces to limits flash size to 0x1000000 (16M). It's normal when first bring up and into linux. However, we find the uboot is broken or overrided and can…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • STRD ATOMIC?

    loquat
    loquat

    Hi, I make a software for Cortex-A9 and Cortex-M4 (both uni-processor system).

    Question.

    Is 64bit-aligned STRD(64bit memory access) atomic ?

    (I know tha It is not atomic, but i don't know behavior.)

    For example:

    LDR R2,=buff

    mov R0, #1

    mov R1, #2

    STRD R0…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A9 PMU cycle counter not always incrementing at CPU frequency?

    Christian Ascheberg
    Christian Ascheberg

    Hello,

    I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU frequency scaling is active, which is confusing me…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • cross compiling the hello trust zone example

    Sean
    Sean

    Is it possible for me to cross compile the hello Trust Zone example referenced here: Cortex-A9 TrustZone example ? The build file contains the command options for the arm compiler. I do not have the board this example was meant for, and I am trying to…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Feature wise comparision for Cortex A series processors

    techguyz
    techguyz

    Hi Experts,

    Is there any document on feature wise comparison chart on the Cortex A series of processors ?

    Like,

    Cache for Cortex A8/9/52...

    MMU for cortex A8/9/52..

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cache maintanance operation to PoC

    Luke
    Luke

    Hi experts,

    I'm quite confused about cache maintanance operation to PoC on Cortex-A9 (with PL310 L2 cache controller).

    I'm refererring to the following operations:

    - DCIMVAC, invalidate data cache by MVA to POC      (mcr  p15, 0, r0, c7, c6, 1)…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex A9 flush cache

    Tamilselvan Shanmugam
    Tamilselvan Shanmugam

    I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements.

    Is it doable from user mode?

    Processor: ARM Cortex A9

    OS: Linaro Linux

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Issue with WatchDog reset De-asserting

    BAB
    BAB

    Hi,

    I am working on ARM CortexA9 processor. I could able to enable both l4wd0 and l4wd1 watchdogs. Issue is system is resetting but not rerunning. I tried changing the register values of reset Manger as well.

    How to de-assert the reset and make the system…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Watchdog timer not entering ISR

    sherry
    sherry

    I am using ARM cortex A9 core in Zynq. I want to trap any bugs in hardware or my firmware. I intend to use watchdog module in interrupt mode and connect it to Global interrupt controller (ScuGic). When the watchdog counter decrements to zero, it is to…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • dump MMU translation table for A9 in Linux

    mivascu
    mivascu

    Hello,

         I would like to know how to read the translation table info for A9  from embedded Linux.

         In freeRTOS I have translation_table.S but I do not find anything similar for ARM architecure in linux kernel.

         Should I just dump TTBR0/TTBR1 registers…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • MMU initialization for an ARM multicore system

    ddn
    ddn

    I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib).

    On the shared SDRAM, I am planning to have dedicated memory regions for each core, and a shared…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • A9 Code after vector table

    josecm
    josecm

    I am implementing a small OS as a university project in a A9 chip (a Xilinx Zynq). I am using trustzone to implement some features and I want to pass through SVC calls from user mode directly to monitor, so I issue an SMC in my SVC handler. Here it is…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv7 CortexA9 Cache Policy - No allocate ?

    josecm
    josecm

    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A kind of write-through / "no-allocate" policy?…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Can Floating Point Unit(FPU) in cortexA9 processor raise an exception?

    Yeli
    Yeli

    Based on  ARM documents there is no exception ID for FPU (CortexA9) and just FPU instructions set exception flags in Floating-Point Status and Control Register (FPSCR). Is there a way to use these flags to raise an exception in the processor?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Which is better of thees CPUs

    kasem
    kasem

    Which is better of thees CPUs:

    Cortex A53 octa core 1.5 ghz,

    Cortex A7 Allwinner T8 Eight core 2.0 ghz,

    Cortex A9 Quad-Core 1.8 ghz ?

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Non-Cacheable memory and DMA on armv7a

    Vincent Siles
    Vincent Siles

    Hi !

    Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0).

    We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro kernel allocate some memory to the user application…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ACP and DMA usage on A53

    leslielg
    leslielg

    Hi,

    I'm using DMA transfering data through ACP on A53. 

    According to A53 TRM, ACP burst size limits to 16B and 64B, does it mean the DMA connect to ACP also limited to transfer 64B data in max each time?

    Then software must re-configure DMA then re…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • MRS [A/C]PSR latency armv8-a?

    MarkL
    MarkL

    HI,

    Do anyone has a clue on the latency of the MRS CPSR (or APSR) command?

    I want to read the flags with no jump (and it is critical).

    Thanks

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Memory read error at 0xF8000008: Cannot read write-only register.

    doner_t
    doner_t

    Hello, 

    I am not sure, here is correct place to ask this question. But I want to try ; 

    I have received an error :  Memory read error at 0xF8000008: Cannot read write-only register, When I try to debug a basic memory test code, in CortexA9.  I can not even…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Trying to find basic performance measurements of ARM cores

    eskimoalva
    eskimoalva

    Howdy, I was trying to find some basic performance benchmarks for a couple of different ARM cores: The Arm 926EJ-S, Cortex A9, and the Cortex M7.

    I am looking for primarily DMIPS (per MHz or a form that requires me scaling to my specific chip is fine…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex A9 - Enabling/Disabling the Caches

    M.Eladouly
    M.Eladouly

    Hello,

    I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9).

    In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches, MMU and Program Prediction.

    What I need is to know…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to know if a RAM is compatible with an architecture or a processor?

    wchgoldbach
    wchgoldbach

    I don't have much experience in building an embedded system from 0. I want to ask a general question as showed in the title through an example.

     

    I choose Cortex-A9 (ARMv7-Profile A architecture) as CPU.  Then I want to use DDR3 RAM of Alliance memory…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
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