• Multicore SMP using Linux kernel

    manish
    manish

    Hi,

    I am just trying to learn the linux kernel booting process for arm32 Cortex A9 multi core SOC. I had understood the concept of booting in linux, but I am confused about the section where secondary cores enabling from primary core. Can somebody briefly…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex-A9 | Non-cacheable memory range

    S R Chidrupaya
    S R Chidrupaya
    Note: This was originally posted on 23rd May 2013 at http://forums.arm.com

    Hi all,


    I am designing an application on  xilinx zynq 702 board which comes with two(core) arm cortex a9 processors. I am using one of the arm cores two run a part of the application…
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AXI SLAVE PERIPHERAL

    Antonio
    Antonio

    Hi everyone! Please help me.. i have  a project with a custom axi slave  design that  implements multiple memory ranges 256 words each . A master ( my processor in figure) can write burst data to the example slave and read the data back. The problem is…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Can I build my own ARM board like the raspberry pi

    Joshua Pritsker
    Joshua Pritsker

    Is it possible and if so how can i build my own raspberry pi alike?

    Can I use this AM4378 | AM437x | ARM Cortex-A9 | Description & parametrics ???

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • unaligned data fetch in Cortexa9

    anoop
    anoop

    I have a question related to data fetch, when on gdb debugger I do an address read say as:

    X 0x81000000

    Then it will fetch 64 bits as you told in reference to Cortex A9

    If further I do

    X 0x81000004

    Will it fetch 64 bits  again from 0x81000000 or it will use…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Question -

    Michihiro Yamamoto
    Michihiro Yamamoto

    Hi,

    I have strange symptom with Cortex-A15 device.

    The below is traced data.

    Program AddressDisassembly

    0x40401AA0CMP             R12, R0

    0x40401AA4BHI             0x40401A80…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to handle SCU at runtime on Cortex-A9

    John
    John

    Hi there,

    I'm working on altera cyclone V SoC equipped with a Dual Core Cortex-A9. It runs Linux socfpga 3.13. I'm trying to disable (and enable) the SCU at runtime, but I have a segmantation fault: unable to handle kernel paging requet at virtual address…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A9-PL310 AXI connection

    Luke
    Luke

    Hi experts,

    I would like to know more about the interconnection between Cortex-A9 and the PL310 L2 cache controller.

    I think Figure 1.2 in the TRM is a good starting point:

    CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual: 1.2. Typical…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • what are the main differences between cortex A7, A9, A53

    aaa
    aaa

    What are the main/important features added/updated?

    Thank you.

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • wrong reset value of TTBR0 at reset, in Cortex A9, R3P0

    anoop
    anoop

    Hi

    i have some questions on dual Core CortexA9 r3p0 revision.

    I am using Cortex A9 r3p0 processor in Our SOC(system on Chip). when i connect to Core 0 and read TTBR0 register i get 0x00004001, but when i connect to Core1 and do read the same TTBR0 register…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex 32b/64b processors with Data Trace capability?

    Andreas Koch
    Andreas Koch

    Hello all,

    do any of the faster application processors (Cortex-A9 and up) have data trace capabilities enabled in their on-chip debug logic? I have been looking at both Xilinx and Altera Cortex-A9 cores, and both of them appear to only provide instruction…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Kernel page table makes page fault although other core already mapped.

    Yeo Reum Yun
    Yeo Reum Yun

    Hi, expert. I'm making CacheFlush function by Virtual Address.

    I'm using TTBR0 for user area, and TTBR1 for Kernel Area, and I'm using Dual core, Cortex-A9

    I'm using Cache Flush Policy as Write Through about Kernel PageTable (Below KPT) itself…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • cortex A9 multi-core

    guqintai
    guqintai

    I'm learning cortex-a9 on freescale imx6 platform. How to start multi-core? And how to communicate between cores? I'm confused.

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • TZASC (TZC380) enabling sequence

    Vincent Siles
    Vincent Siles

    Hi everyone, I am trying to correctly setup the TZASC of my IMX6q and IMX6ul boards, without blowing the fuse (I only have one board, I'd like to have it right by software before).

    From what I gathered from the documentation of the TZASC and from the…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Need to invalidate L1 cache after DMA on Cortex A9

    Rohan
    Rohan

    Hi,

    I'm using a Renesas RZ/A1L, Cortex A9 microcontroller. After a DMA operation which transfers some data from a SPI module into RAM, I can't read the data correctly unless I've disabled L1 cache. (The base code which Renesas supplies sets the caches…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Embedded assembly function problem

    Andrea
    Andrea

    Hello all,

    I wrote end embedded assembly function for an ARM Cortex A9 (the specific device is Zynq, from Xilinx) as follow

    float my_fun(float x)

    {

                    asm volatile ("vdup.f32 d0, r0                     \n\t");…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex A9 second execution unit

    Kushal
    Kushal

    Dear All,

    I am trying to understand the full working of execution stage in ARM cortex A9 and the types of instructions that are executed in second execution unit(ALU).

    Till now i was able to find quite limited references that were not much helpful.

    If any…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is it possible to read the raw L1/L2 cache data and tag bits on the Cortex-A9?

    Alex W
    Alex W

    I've been digging through the Technical Reference Manual (TRM) for the Cortex-A9 and so far it seems that it's possible to gather data about events such as hit and miss rates, but there doesn't seem to be anything on reading the raw data and tag bits…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Differences between Privilege Modes and Non-Privilege Mode ?

    Rui
    Rui

    Hi everyone ,

    I'm currently using a Cortex-A9 processor (NXP Freescale i.MX6S).

    My project is to develop a simple OS, but I met a problem:   

    When I am trying to control some peripherals (such as UART and GPIO) directly under ARM USER MODE, the program…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Secure world entry request by normal world application

    Shane Yu
    Shane Yu

    For a TrustZone enabled processor, what if a normal world application (e.g. 3rd party application) directly uses SMC instruction to request a secure world entry? In a typical case, it it a responsibility of monitor SW or Secure OS kernel to authenticate…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • PMU in arm11 results

    Muhammad Ali
    Muhammad Ali

    Hi,

    I am programming raspbery pi model b ARM1176 bare metal (in assembly and c). I need to calculate the clock cycles used to execute an assembly code.

    I am using the following code for PMU counter:

    1.   mov r0,#1 
    2.   MCR p15, 0, r0, c15, c12…
    • Answered
    • 10261.zip
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Locked L2 cache (Pl310) Write issue through JTAG- Zynq 7000

    Abhilash VR
    Abhilash VR

    We are using a Zynq-7000 SoC, and we are trying to do read and write to a locked L2 Cache through JTAG.

    From JTAG, Read works properly but writes makes the specific cache line corrupted,

    Step 1 : Initial Setup

         1. Wrote an application Which runs from…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A9 CPU self-tests

    Daniel Watson
    Daniel Watson

     

    Hi!

    I am currently working in a project with a Freescale i.MX6 (Cortex A9) board. The system has to be certified against the ISO 13849 standard and my job is to implement software diagnostics in accordance to ISO 13849.

    Now my problem is that ISO…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • SMP ARM cores hang when using DMA and two cores enabled

    Elad Nachman
    Elad Nachman

    Hi,

    I am experiencing A complete arm core hang when both of the cores are employed in SMP mode and using DMA.

    I was tested with Linux kernels 3.10, 4.1 and 4.6 in SMP mode.

    SOC used is Altera Cyclone V SOC-FPGA with dual Cortex A9.

    The DMA transfer goes from…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • HI,why the VFP vector mode can not be used in cortex-a series processors?

    fansi
    fansi

    HI,why the VFP vector mode can not be used in cortex-a series processors?

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
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